gEDA-user: [pcb] overlapping pin/pad -- won't form thermal

[Steve Meier]

I haven't tried this but a work around might be to use a polygon rather
then a pad. If you need to solder to the polygon then make a small pad
not connected to the via and open the soldermask clearence but not the
polygon clearance.

Steve M


joe tarantino wrote:
>
>
> On Mon, Mar 10, 2008 at 5:16 PM, Dave N6NZ <n6nz at arrl.net
> <mailto:n6nz at arrl.net>> wrote:
>
>
>     DJ Delorie wrote:
>     >> PCB needs first class support for oblong through-holes.
>     >
>     > Yup.  I've talked about a "multi-pin" before; this is a pin with
>     > arbitrary shaped copper/soldermask/etc on each layer.
>     >
>     Yes, when you get to multi layer boards you often want a different
>     annulus on inner layers.
>
>     I think it's time to think about an expansion to the footprint grammar
>     to support more sophisticated pins and also more sophisticated
>     paste specs.
>
>     -dave
>
> Without piling on too much....
>
> - Expanding the grammar to support inner layer pad <> outer layer pad
> would be great.  (Would one geometry definition apply to all inner
> layers?)
> - Also consider whatever would allow pins (and vias) with no
> connection to some layers (maybe supporting blind and buried vias in
> the process?)
> - Taking this too the limit, consider a shift to a more heirarchical
> approach which would allow pad definitions to be "included" in a
> footprint by reference rather than direct inclusion.
> (My ignorance of the data structures now used by PCB may be evident
> here - I don't know how difficult this would be).
>
> Joe T
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