gEDA-user: [PCB] Bug? Silk tracks clear poly on file reload

[Dave N6NZ]

Using a version of PCB build from CVS during December that advertises 
itself as version 1.99w, I find that tracks drawn on back silk block 
polygons, but only when the file is reloaded. (I didn't try polys on 
front, it might also have a problem.)

To reproduce:
1) create polygon on back copper.
2) draw a line through the polygon on back silk.
3) export exactly the correct gerber that you would expect.
4) save the layout and quit pcb.
5) reload the file into pcb
6) observe that the silk track has plowed the copper and disconnected 
the two halves of the polygon.

Is this an old bug that I managed to capture out of CVS, or is it still 
there?

The work-around is to turn off "new lines clear poly" when drawing silk. 
But this is a pretty ugly bug, since you get the correct behavior until 
you save and reload the file, at which point your design has been h0rk3d up.

-dave