gEDA-user: iverilog: Nonstandard Macro Expansion

[lingwitt at bellsouth.net]

I recently found out (painfully) that an intuitive
and excellent feature of iverilog is nonstandard.

The OVI reference manual states:

The text specified for <MACRO_TEXT> must not be split across the  
following lexical tokens:
	* comments
	* numbers
	* strings
	* identifiers
	* keywords
	* double  or  triple  character  operators

However, iverilog supports "splitting" across at
least identifiers. For instance, the following is
possible with iverilog:

     `define Name IsTerrible

     module Verilog`Name(...);
         ...
     endmodule

which is preprocessed before compilation into:

     module VerilogIsTerrible(...);
         ...
     endmodule


Such code is impossible in commercial tools like
Xilinx's synthesizer.


Should iverilog continue to support this kind of
behavior?




>> The burden is on the programmer, not
>> the tools.

This is another classic example.


>> However, the lack of such a feature shows
>> the poor thought of Verilog's designers.
>
> This is a bit too glib for my tastes.... I don't think it's quite  
> fair for you
> to assume you know so much more (or are so much smarter then) the
> people who were there.

I don't care what anybody says. These people didn't think much.