gEDA-user: iVerilog's Strengths [bug?]

[lingwitt at bellsouth.net]

I've been having trouble with strengths.

I think there may be a bug, unless I'm
using them incorrectly.

Consider:
	
	module test;
         tri blah;

         assign (pull1, strong0) blah = 0 ? 0 : 1;
         assign blah = 0;

         initial
             $display("Blah should be 0: %d", blah);
     endmodule

Output:

     Blah should be 0: x


However, using a temporary works:

     module test;
         tri blah;

         wire blahTemp = 0 ? 0 : 1;

         assign (pull1, strong0) blah = blahTemp;
         assign blah = 0;

         initial
             $display("Blah should be 0: %d", blah);
     endmodule

Output:

     Blah should be 0: 0


Also, I'm assuming that strengths are carried around
with the value. Is this the case?

Thanks.