gEDA-user: Re: iverilog: Parameters of Parameters

[lingwitt at bellsouth.net]

On 1 May 2007, at 4:02:28 AM, Evan Lavelle wrote:

> Stephen Williams wrote:
>> lingwitt-Bdlq13kUjeyLZ21kGMrzwg at public.gmane.org wrote:
>>> Basically, I'm whining for a feature.
>> I've looked at the thread in comp.lang.verilog. The parameter
>> definition circularity problem is nasty, but a carefully contained
>> extension (a la the way Modelsim handles it) seems plausible.
>> This is a good candidate for the Feature Request list, I think.
>
> But it's not valid Verilog. If you start adding nice features that  
> aren't in the LRM, and aren't supported in the reference compilers,  
> where will it all end?
>
> ...in VHDL, perhaps?
>
> [sorry, couldn't resist... :)]

If we all blindly follow bad standards, where will it all end?

...in Verilog, perhaps?

[sorry, couldn't resist... :)]


In any case, as I stated in my last email,
this feature probably isn't good to add,
strictly because it seems to be nonstandard.

However, the lack of such a feature shows
the poor thought of Verilog's designers.

The burden is on the programmer, not
the tools.
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