gEDA-user: Polygon clearance around a hole

[Justyn Butler]

PCB version: 20060822

So this was a bug that's been fixed in the CVS version?

cheers,
Justyn

On 22/02/07, DJ Delorie <dj at delorie.com> wrote:
>
>
> > It doesn't seem to be possible to have polygon clearance around an
> > unplated via (a via with the "hole" flag).
>
> What version of pcb?  It seems to work ok in cvs.
>
>
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