gEDA-user: VLSI Chip Design Software

[Peter TB Brett]

Hi folks,

I just ran across something on the internet that I thought might be 
interesting to list members:

  Alliance VLSI CAD System
  http://www-asim.lip6.fr/recherche/alliance/

This is a full GPLed chip design system.

A couple of (very uninformed) observations:

 - It appears to be digital-only.

 - It seems to rely very heavily on algorithmic place and route with hints
   provided by the designer. 

 - An immediate turn-off is that it uses the Synopsys VHDL subset (ugh).  To
   make matters worse, you have to use specific VHDL subsets for different
   parts of the device; no design inference.

 - It looks _very_ similar to the Cadence VLSI tools (more or less a clone, I
   suspect).

 - The schematic and waveforms don't look very friendly; it would be nice to
   investigate whether Alliance could be persuaded to use gschem and gtkwave
   instead (maybe via an unofficial add-on).

Cheers,

                         Peter
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