gEDA-user: bypass caps

[DJ Delorie]

> I feel like I'm beating this horse far beyond the point where it's
> already dead. . . . . .

But I'm still learning stuff, so I'm OK with it.

> But I looked at your most recent layout, and another question
> occurred to me: Is there a reason you are using long, spindly traces
> [1] for VCC/GND, and not using great big polygons (areafills) [2]?

I thought of that.  I'm still tweaking the layout a little, and
managing the polygons is hard (and slow) with complex boards.

> [2] Besides the fact that doing areafills using PCB is still a PITA,
> that is . . . .

:-P