gEDA-user: bypass caps

[Stuart Brorson]

> I'm working on a simple sram/ethernet add-on card for one of my m32c
> starter kits.  It's a 2 layer 3.5x4.5 board, 32MHz signalling, and the
> power and ground are "tree structure" - i.e. no planes (won't fit) -
> with 20 mil traces (signals are 8 mil).  Heck power and ground enter
> the board about 3" apart on the connector!  (yes, they put one on each
> end).  This fab will also have the challenge boards on it, so 4 layer
> is not an option.

Yuck!  No GND plane!  How barbaric!  How '70s!

I believe that back in the 70s DEC used to use two layer boards with
PWR and GND run on busses layed out on a rectilinear grid.  Signal
traces were on top (IIRC) and PWR/GND on teh bottom.  The DIPs
were layed out in rectangular rows following teh same grid.  Fingers
would extend from the PWR and GND busses to each DIP to feed
its power/ground pins.

If you adopt that approach, then you should put some big tantalum caps
between the PWR and GND busses at the end of each component row.
Then, at each component use a 0.1uF ceramic cap to bypas each chip.
Here's some ASCII art describing the scheme:

VCC           GND   Feed point
##            ##
##    ||      ##
##----||------##    10uF tant
##    ||      ##
##            ##
##            ##
##----||------##    .1uF ceramic
##   ----- #####
##   |   |    ##
##   |   |    ##
##   |   |    ##
#####-----    ##
##            ##
##            ##
##----||------##     .1 uF ceramic
##   ----- #####
##   |   |    ##
##   |   |    ##
##   |   |    ##
#####-----    ##
##            ##
##            ##
VCC           GND   Feed point

I won't guarantee that it is the optimal layout, particularly for a
high-speed board, but it's what the folks at DEC used to do back in
the day.

Stuart