gEDA-dev: Re: icarus verilog wor net simulation question

[Lennert Buytenhek]

On Thu, May 17, 2007 at 10:50:45AM -0700, Stephen Williams wrote:

> > 	module blah ( in, out );
> > 		input	in;
> > 		output	out;
> > 
> > 		assign out = in;
> > 	endmodule
> > 
> > 	module top;
> > 		wor	total;
> > 
> > 		blah blah1 ( 1'b0, total );
> > 		blah blah2 ( 1'b1, total );
> > 	endmodule
> > 
> > Reading the value of blah1.in gives me, confusingly, a 1.
> 
> Does Icarus Verilog even support wor? Hmmm, I think it does.
> It is possible that it does what you say, I can't tell from
> memory. The way to find out is to look at the vvp output.
> It appears as you say that in and out wind up wired together
> since the assign is acting like a net joint.
> 
> It is a little confusing, and maybe even wrong, but the
> output is right, and if you drove the ports with non-constant
> values you'd get different results.

If I drive a single wor net with different non-constant values
(0/1), the value of the net seems to become undefined in some
cases (i.e.  doesn't happen with every combination of inputs,
in some cases it does give the expected results.)

I decided to just recode my code to get rid of the wor nets,
which means I can inspect the state of all the driving nets
now, and I don't see spurious undefined values anymore.