gEDA-dev: icarus verilog wor net simulation question

[Kev Cameron]

Lennert Buytenhek wrote:
> Hi,
>
> I didn't see this in the FAQ or in a quick browse of the mailing list
> archives, but feel free to flame me if this has been asked before.
>
> I have the following code.
>
> 	module blah ( in, out );
> 		input	in;
> 		output	out;
>
> 		assign out = in;
> 	endmodule
>
> 	module top;
> 		wor	total;
>
> 		blah blah1 ( 1'b0, total );
> 		blah blah2 ( 1'b1, total );
> 	endmodule
>
> Reading the value of blah1.in gives me, confusingly, a 1.
>
> What I'm guessing is happening is that due to the assign, blah1.in,
> blah1.out, blah2.in and blah2.out end up being merged into the same
> net.
>
> I understand that it's not easy in a hardware implementation to find
> out which of the inputs or a wor net is causing the net to be driven
> high, but it would be nice if the simulator could give me this info.
>   
Have a look at Verilog-AMS: in order to correctly convert digital 
drivers to analog contributions (currents) on mixed-signal nets it has 
routines for scanning the drivers of a net. 
http://www.eda.org/verilog-ams/htmlpages/lit.html

Hope that helps,
Kev.

> If I change the assign to the following, I do get the info I'm
> looking for (probably due to defeating some optimisation.)
>
> 	assign out = ~(~in);
>
> Is where a way of achieving the same result without having to add
> ~(~x) hacks?
>
> (Using Icarus verilog 0.8.4 on a Linux box, using gtkwave to look
> at the VCDs.)
>
>
> thanks,
> Lennert
>
>
> _______________________________________________
> geda-dev mailing list
> geda-dev at moria.seul.org
> http://www.seul.org/cgi-bin/mailman/listinfo/geda-dev
>