gEDA-dev: icarus verilog clock edge at t=0 question

[Lennert Buytenhek]

Thanks for taking the time to reply.


On Wed, May 16, 2007 at 03:46:30PM -0500, John Griessen wrote:

> > it seems that submodule_rising becomes 1'b1 at t=1, so
> > somehow it is picking up a posedge clk at t=0.
> 
> I see it defined at time zero in two ways -- wire from sub and
> reg inside sub. Maybe one is X at t=zero?

Hmm, possible.

If I do:

	reg clk = 1'b1;
	wire clk2 = clk;

	initial clk = 1'b1;

Then I do see a posedge on clk2 at t=0, but not on clk.  I guess
in a way that makes sense.


> > topmodule_rising does _not_ seem to pick up a posedge clk at t=0,
> > so that signal _does_ only become 1'b1 at t=11.
> 
> topmodule_rising is defined a 1 at t=zero and stays 1, so no edge.

(If you mean s/topmodule_rising/clk/, then yeah.)


thanks,
Lennert