gEDA-dev: icarus verilog wor net simulation question

[Lennert Buytenhek]

Hi,

I didn't see this in the FAQ or in a quick browse of the mailing list
archives, but feel free to flame me if this has been asked before.

I have the following code.

	module blah ( in, out );
		input	in;
		output	out;

		assign out = in;
	endmodule

	module top;
		wor	total;

		blah blah1 ( 1'b0, total );
		blah blah2 ( 1'b1, total );
	endmodule

Reading the value of blah1.in gives me, confusingly, a 1.

What I'm guessing is happening is that due to the assign, blah1.in,
blah1.out, blah2.in and blah2.out end up being merged into the same
net.

I understand that it's not easy in a hardware implementation to find
out which of the inputs or a wor net is causing the net to be driven
high, but it would be nice if the simulator could give me this info.

If I change the assign to the following, I do get the info I'm
looking for (probably due to defeating some optimisation.)

	assign out = ~(~in);

Is where a way of achieving the same result without having to add
~(~x) hacks?

(Using Icarus verilog 0.8.4 on a Linux box, using gtkwave to look
at the VCDs.)


thanks,
Lennert