March 2007 Archives by author

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Starting: Thu Mar 1 00:11:59 EDT 2007
Ending: Sat Mar 31 21:51:18 EDT 2007
Messages: 374

• gEDA-dev: EDIF docs?   Carlos Nieves Ónega
• gEDA-dev: Help in apply SoC2007   André Costa
• gEDA-dev: Google summer of code   Günter Dannoritzer
• gEDA-dev: Re: Google summer of code   Günter Dannoritzer
• Icarus Verilog Graffiti; was Re: gEDA-dev: Re: Google summer of code   Günter Dannoritzer
• Icarus Verilog projects in academic; was Re: gEDA-dev: Google summer of code   Günter Dannoritzer
• Icarus Verilog projects in academic; was Re: gEDA-dev: Google summer of code   Günter Dannoritzer
• Icarus Verilog projects in academic; was Re: gEDA-dev: Google summer of code   Günter Dannoritzer
• gEDA-dev: SoC: Gerber, DRC, gsch2pcb and D-BUS   Mike Jarabek
• gEDA-dev: Google summer of code   David Baird
• gEDA-dev: Google summer of code   David Baird
• gEDA-dev: Google summer of code   David Baird
• gEDA-dev: C question   David Baird
• gEDA-dev: x_compselect.c   Felipe Balbi
• gEDA-dev: gnetman inspired libgeda datastructures   Svenn Are Bjerkem
• gEDA-dev: waveform viewer, collected some notes in the wiki   Svenn Are Bjerkem
• gEDA-dev: Re: VHDL as a file format   Svenn Are Bjerkem
• gEDA-dev: SoC: Gerber, DRC, gsch2pcb and D-BUS   Svenn Are Bjerkem
• gEDA-dev: SoC: Gerber, DRC, gsch2pcb and D-BUS   Svenn Are Bjerkem
• gEDA-dev: SoC: Gerber, DRC, gsch2pcb and D-BUS   Svenn Are Bjerkem
• gEDA-dev: Google summer of code   Anthony Blake
• gEDA-dev: topological routing path search algorithms   Anthony Blake
• gEDA-dev: topological routing path search algorithms   Anthony Blake
• gEDA-dev: Icarus Verilog and Xilinx unisim files   Uwe Bonnes
• gEDA-dev: Re: Icarus Verilog and Xilinx unisim files   Uwe Bonnes
• gEDA-dev: Re: Icarus Verilog and Xilinx unisim files   Uwe Bonnes
• gEDA-dev: Re: gEDA-user: scons   Peter TB Brett
• gEDA-dev: Pinning down libgeda   Peter TB Brett
• gEDA-dev: XML File Formats, hierarchy issues and other rants   Peter TB Brett
• gEDA-dev: XML File Formats, hierarchy issues and other rants   Peter TB Brett
• gEDA-dev: Souce Contreol of big architectural projects in GoogleSoC....   Peter TB Brett
• gEDA-dev: XML File Formats, hierarchy issues and other rants   Peter TB Brett
• gEDA-dev: SoC Hopeful   Peter TB Brett
• gEDA-dev: topological routing path search algorithms   Peter TB Brett
• gEDA-dev: google SOC   Stuart Brorson
• gEDA-dev: Google summer of code   Stuart Brorson
• gEDA-dev: Call for Google SoC Mentors!   Stuart Brorson
• gEDA-dev: April code sprint announcement!   Stuart Brorson
• gEDA-dev: PCB: escape key   Stuart Brorson
• gEDA-dev: Hi... question about refdes_renum   Stuart Brorson
• gEDA-dev: Hi... question about refdes_renum   Stuart Brorson
• gEDA-dev: XML File Formats, hierarchy issues and other rants   Stuart Brorson
• gEDA-dev: Rant on GPL confussion in regards to geda symbols   Stuart Brorson
• gEDA-dev: XML File Formats, hierarchy issues and other rants   Stuart Brorson
• gEDA-dev: GPL clarification text -- please review & comment/flame!   Stuart Brorson
• gEDA-dev: GPL clarification text -- please review & comment/flame!   Stuart Brorson
• gEDA-dev: Rant on GPL confussion in regards to geda symbols   Stuart Brorson
• gEDA-dev: Revised symbol license text   Stuart Brorson
• gEDA-dev: Revised symbol license text   Stuart Brorson
• gEDA-dev: SoC Hopeful   Stuart Brorson
• gEDA-dev: gnetman inspired libgeda datastructures   Stuart Brorson
• VHDL, was Re: gEDA-dev: Hierarchical buses   Stuart Brorson
• gEDA-dev: SoC: Gerber, DRC, gsch2pcb and D-BUS   Stuart Brorson
• gEDA-dev: SoC: Gerber, DRC, gsch2pcb and D-BUS   Stuart Brorson
• gEDA-dev: Bug reports for gattrib   Stuart Brorson
• gEDA-dev: SoC: Gerber, DRC, gsch2pcb and D-BUS   Justyn Butler
• gEDA-dev: SoC: Gerber, DRC, gsch2pcb and D-BUS   Justyn Butler
• gEDA-dev: SoC: Gerber, DRC, gsch2pcb and D-BUS   Justyn Butler
• gEDA-dev: SoC: Gerber, DRC, gsch2pcb and D-BUS   Justyn Butler
• gEDA-dev: SoC: Gerber, DRC, gsch2pcb and D-BUS   Justyn Butler
• gEDA-dev: SoC: Gerber, DRC, gsch2pcb and D-BUS   Justyn Butler
• gEDA-dev: Re: VHDL, was Re: Hierarchical buses   Anthony J Bybell
• gEDA-dev: Revised symbol license text   David Cary
• gEDA-dev: Pinning down libgeda   Peter Clifton
• gEDA-dev: PCB - XY values of centrioid in BOM/DXF exproter (was gEDA-user: PCB Element for a Molex 71661-2068?)   Peter Clifton
• gEDA-dev: Souce Contreol of big architectural projects in Google SoC....   Peter Clifton
• gEDA-dev: Peripheral SoC Project ideas   Peter Clifton
• gEDA-dev: Souce Contreol of big architectural projects in GoogleSoC....   Peter Clifton
• gEDA-dev: Peripheral SoC Project ideas   Peter Clifton
• gEDA-dev: Patches on sourceforge   Peter Clifton
• gEDA-dev: Google SoC Announcement   Peter Clifton
• gEDA-dev: Google SoC Announcement   Peter Clifton
• gEDA-dev: Google SoC Announcement   Peter Clifton
• gEDA-dev: Souce Contreol of big architectural projects inGoogleSoC....   Peter Clifton
• gEDA-dev: Revised symbol license text   Peter Clifton
• gEDA-dev: Further thoughts on Parts Manager   Peter Clifton
• gEDA-dev: Further thoughts on Parts Manager   Peter Clifton
• gEDA-dev: SoC Hopeful   Peter Clifton
• gEDA-dev: SoC Hopeful   Peter Clifton
• gEDA-dev: SoC Hopeful   Peter Clifton
• gEDA-dev: SoC Hopeful   Peter Clifton
• gEDA-dev: gnetman inspired libgeda datastructures   Peter Clifton
• gEDA-dev: gnetman inspired libgeda datastructures   Peter Clifton
• gEDA-dev: Hierarchical buses   Peter Clifton
• VHDL, was Re: gEDA-dev: Hierarchical buses   Peter Clifton
• VHDL, was Re: gEDA-dev: Hierarchical buses   Peter Clifton
• gEDA-dev: gnetman inspired libgeda datastructures   Peter Clifton
• VHDL, was Re: gEDA-dev: Hierarchical buses   Peter Clifton
• gEDA-dev: New diagram (attempt at UML)   Peter Clifton
• gEDA-dev: New diagram (attempt at UML)   Peter Clifton
• gEDA-dev: New diagram (attempt at UML)   Peter Clifton
• gEDA-dev: New diagram (attempt at UML)   Peter Clifton
• gEDA-dev: New diagram (attempt at UML)   Peter Clifton
• gEDA-dev: New diagram (attempt at UML)   Peter Clifton
• gEDA-dev: New diagram (attempt at UML)   Peter Clifton
• gEDA-dev: New diagram (attempt at UML)   Peter Clifton
• gEDA-dev: New diagram (attempt at UML)   Peter Clifton
• gEDA-dev: New diagram (attempt at UML)   Peter Clifton
• gEDA-dev: New diagram (attempt at UML)   Peter Clifton
• Hidden Nets Re: gEDA-dev: New diagram (attempt at UML)   Peter Clifton
• gEDA-dev: New diagram (attempt at UML)   Peter Clifton
• gEDA-dev: SoC: Gerber, DRC, gsch2pcb and D-BUS   Peter Clifton
• gEDA-dev: New diagram (attempt at UML)   Peter Clifton
• gEDA-dev: SoC: Gerber, DRC, gsch2pcb and D-BUS   Peter Clifton
• gEDA-dev: SoC: Gerber, DRC, gsch2pcb and D-BUS   Peter Clifton
• gEDA-dev: Noscreen branch   Peter Clifton
• gEDA-dev: Noscreen branch   Peter Clifton
• gEDA-dev: Bug reports for gattrib   Peter Clifton
• gEDA-dev: proposed changes to drag on PCB   Peter Clifton
• gEDA-dev: New wiki page about data structure   Peter Clifton
• gEDA-dev: Revised symbol license text   Cory Cross
• gEDA-dev: My multiple footprint plan   Cory R. Cross
• gEDA-dev: Revised symbol license text   Cory R. Cross
• gEDA-dev: Regarding SoC application   Scott Dattalo
• gEDA-dev: Google summer of code   DJ Delorie
• gEDA-dev: Google summer of code   DJ Delorie
• gEDA-dev: pcb bug 1651335   DJ Delorie
• gEDA-dev: PCB: escape key   DJ Delorie
• gEDA-dev: Rant on GPL confussion in regards to geda symbols   DJ Delorie
• gEDA-dev: Rant on GPL confussion in regards to geda symbols   DJ Delorie
• gEDA-dev: Rant on GPL confussion in regards to geda symbols   DJ Delorie
• gEDA-dev: GPL clarification text -- please review & comment/flame!   DJ Delorie
• gEDA-dev: GPL clarification text -- please review & comment/flame!   DJ Delorie
• gEDA-dev: Google SoC Announcement   DJ Delorie
• gEDA-dev: GPL clarification text -- please review & comment/flame!   DJ Delorie
• gEDA-dev: debugging Gtk-WARNING **:Invalid input string   DJ Delorie
• gEDA-dev: GPL clarification text -- please review & comment/flame!   DJ Delorie
• gEDA-dev: GPL clarification text -- please review & comment/flame!   DJ Delorie
• gEDA-dev: GPL clarification text -- please review & comment/flame!   DJ Delorie
• gEDA-dev: GPL clarification text -- please review & comment/flame!   DJ Delorie
• gEDA-dev: GPL clarification text -- please review & comment/flame!   DJ Delorie
• gEDA-dev: GPL clarification text -- please review & comment/flame!   DJ Delorie
• gEDA-dev: SoC Hopeful   DJ Delorie
• gEDA-dev: SoC Hopeful   DJ Delorie
• gEDA-dev: SoC Hopeful   DJ Delorie
• gEDA-dev: SoC: Gerber, DRC, gsch2pcb and D-BUS   DJ Delorie
• gEDA-dev: topological routing path search algorithms   DJ Delorie
• gEDA-dev: topological routing path search algorithms   DJ Delorie
• gEDA-dev: New diagram (attempt at UML)   DJ Delorie
• gEDA-dev: New diagram (attempt at UML)   DJ Delorie
• gEDA-dev: New diagram (attempt at UML)   DJ Delorie
• gEDA-dev: New diagram (attempt at UML)   DJ Delorie
• gEDA-dev: SoC: Gerber, DRC, gsch2pcb and D-BUS   DJ Delorie
• gEDA-dev: SoC: Gerber, DRC, gsch2pcb and D-BUS   DJ Delorie
• gEDA-dev: Regarding SoC application   DJ Delorie
• gEDA-dev: proposed changes to drag on PCB   DJ Delorie
• gEDA-dev: Revised symbol license text   DJ Delorie
• gEDA-dev: proposed changes to drag on PCB   DJ Delorie
• VHDL, was Re: gEDA-dev: Hierarchical buses   Udi Finkelstein
• VHDL, was Re: gEDA-dev: Hierarchical buses   Udi Finkelstein
• VHDL, was Re: gEDA-dev: Hierarchical buses   Udi Finkelstein
• VHDL, was Re: gEDA-dev: Hierarchical buses   Udi Finkelstein
• gEDA-dev: PCB - XY values of centrioid in BOM/DXF exproter (was gEDA-user: PCB Element for a Molex 71661-2068?)   John Griessen
• gEDA-dev: PCB - XY values of centrioid in BOM/DXF exproter (wasgEDA-user: PCB Element for a Molex 71661-2068?)   John Griessen
• gEDA-dev: PCB: escape key   John Griessen
• gEDA-dev: PCB: escape key   John Griessen
• gEDA-dev: Hi... question about refdes_renum   John Griessen
• gEDA-dev: sch2svg converter needed   John Griessen
• gEDA-dev: Hi... question about refdes_renum   John Griessen
• gEDA-dev: hierarchy and multipart symbols (several with same refdes)   John Griessen
• gEDA-dev: Google SoC Announcement   John Griessen
• gEDA-dev: Revised symbol license text   John Griessen
• gEDA-dev: Further thoughts on Parts Manager   John Griessen
• gEDA-dev: Further thoughts on Parts Manager   John Griessen
• gEDA-dev: new wiki section added for approval by Kurt   John Griessen
• gEDA-dev: SoC Hopeful   John Griessen
• gEDA-dev: gnetman inspired libgeda datastructures   John Griessen
• gEDA-dev: Hierarchical buses   John Griessen
• VHDL, was Re: gEDA-dev: Hierarchical buses   John Griessen
• VHDL, was Re: gEDA-dev: Hierarchical buses   John Griessen
• VHDL, was Re: gEDA-dev: Hierarchical buses   John Griessen
• gEDA-dev: SoC: Gerber, DRC, gsch2pcb and D-BUS   John Griessen
• gEDA-dev: Regarding SoC application   John Griessen
• gEDA-dev: proposed changes to drag on PCB   John Griessen
• gEDA-dev: Google summer of code   Werner Hoch
• gEDA-dev: sch2svg converter needed   Werner Hoch
• gEDA-dev: sch2svg converter needed   Werner Hoch
• gEDA-dev: waveform viewer, collected some notes in the wiki   Werner Hoch
• gEDA-dev: topological routing path search algorithms   Werner Hoch
• gEDA-dev: geda-doc package has some redundant files   Ales Hvezda
• gEDA-dev: Pinning down libgeda   Ales Hvezda
• gEDA-dev: sch2svg converter needed   Ales Hvezda
• gEDA-dev: Rant on GPL confussion in regards to geda symbols   Ales Hvezda
• gEDA-dev: Rant on GPL confussion in regards to geda symbols   Ales Hvezda
• gEDA-dev: debugging Gtk-WARNING **:Invalid input string   Ales Hvezda
• gEDA-dev: More GSoC project ideas added   Ales Hvezda
• gEDA-dev: More GSoC project ideas added   Ales Hvezda
• gEDA-dev: Patches on sourceforge   Ales Hvezda
• gEDA-dev: Souce Contreol of big architectural projects   Ales Hvezda
• gEDA-dev: SoC Hopeful   Ales Hvezda
• VHDL, was Re: gEDA-dev: Hierarchical buses   Ales Hvezda
• VHDL, was Re: gEDA-dev: Hierarchical buses   Ales Hvezda
• VHDL, was Re: gEDA-dev: Hierarchical buses   Ales Hvezda
• gEDA-dev: Re: gEDA-user: scons   Igor2
• gEDA-dev: Google summer of code   Igor2
• gEDA-dev: Google summer of code   Igor2
• gEDA-dev: Google summer of code   Igor2
• gEDA-dev: GPL clarification text -- please review & comment/flame!   Igor2
• gEDA-dev: SoC Hopeful   Igor2
• gEDA-dev: SoC: Gerber, DRC, gsch2pcb and D-BUS   Mike Jarabek
• gEDA-dev: GPL clarification text -- please review & comment/flame!   Bernd Jendrissek
• gEDA-dev: GPL clarification text -- please review & comment/flame!   Bernd Jendrissek
• gEDA-dev: GPL clarification text -- please review & comment/flame!   Bernd Jendrissek
• gEDA-dev: GPL clarification text -- please review & comment/flame!   Bernd Jendrissek
• gEDA-dev: Regarding SoC application   Lars Johannesen
• gEDA-dev: Regarding SoC application   Lars Johannesen
• gEDA-dev: Regarding SoC application   Lars Johannesen
• gEDA-dev: Re: VHDL as a file format   Evan Lavelle
• VHDL, was Re: gEDA-dev: Hierarchical buses   Evan Lavelle
• VHDL, was Re: gEDA-dev: Hierarchical buses   Evan Lavelle
• gEDA-dev: PCB: escape key   John Luciani
• gEDA-dev: Hi... question about refdes_renum   John Luciani
• gEDA-dev: Rant on GPL confussion in regards to geda symbols   John Luciani
• gEDA-dev: Further thoughts on Parts Manager   John Luciani
• gEDA-dev: More GSoC project ideas added   John Luciani
• gEDA-dev: Pinning down libgeda   Dan McMahill
• gEDA-dev: Google summer of code   Dan McMahill
• gEDA-dev: google SOC   Dan McMahill
• gEDA-dev: Google summer of code   Dan McMahill
• gEDA-dev: PCB - XY values of centrioid in BOM/DXF exproter (was gEDA-user: PCB Element for a Molex 71661-2068?)   Dan McMahill
• gEDA-dev: PCB: escape key   Dan McMahill
• gEDA-dev: PCB: escape key   Dan McMahill
• gEDA-dev: PCB: gtk testers needed   Dan McMahill
• gEDA-dev: Google SoC Announcement   Dan McMahill
• gEDA-dev: PCB: gtk testers needed   Dan McMahill
• gEDA-dev: debugging Gtk-WARNING **:Invalid input string   Dan McMahill
• gEDA-dev: GPL clarification text -- please review & comment/flame!   Dan McMahill
• gEDA-dev: GPL clarification text -- please review & comment/flame!   Dan McMahill
• gEDA-dev: Google SOC suggestion for students   Dan McMahill
• gEDA-dev: SoC Hopeful   Dan McMahill
• gEDA-dev: SoC Hopeful   Dan McMahill
• gEDA-dev: SoC Hopeful   Dan McMahill
• gEDA-dev: SoC Hopeful   Dan McMahill
• gEDA-dev: SoC: Gerber, DRC, gsch2pcb and D-BUS   Dan McMahill
• gEDA-dev: SoC: Gerber, DRC, gsch2pcb and D-BUS   Dan McMahill
• gEDA-dev: Pinning down libgeda   Steve Meier
• gEDA-dev: Pinning down libgeda   Steve Meier
• gEDA-dev: April code sprint announcement!   Steve Meier
• gEDA-dev: Hi... question about refdes_renum   Steve Meier
• gEDA-dev: gschem Write PNG output Issue   Steve Meier
• gEDA-dev: Hi... question about refdes_renum   Steve Meier
• gEDA-dev: XML File Formats, hierarchy issues and other rants   Steve Meier
• gEDA-dev: DRC   Steve Meier
• gEDA-dev: Rant on GPL confussion in regards to geda symbols   Steve Meier
• gEDA-dev: Rant on GPL confussion in regards to geda symbols   Steve Meier
• gEDA-dev: Rant on GPL confussion in regards to geda symbols   Steve Meier
• gEDA-dev: GPL clarification text -- please review & comment/flame!   Steve Meier
• gEDA-dev: GPL clarification text -- please review & comment/flame!   Steve Meier
• gEDA-dev: GPL clarification text -- please review & comment/flame!   Steve Meier
• gEDA-dev: GPL clarification text -- please review & comment/flame!   Steve Meier
• gEDA-dev: GPL clarification text -- please review & comment/flame!   Steve Meier
• gEDA-dev: GPL clarification text -- please review & comment/flame!   Steve Meier
• gEDA-dev: GPL clarification text -- please review & comment/flame!   Steve Meier
• gEDA-dev: SoC Hopeful   Steve Meier
• gEDA-dev: New diagram (attempt at UML)   Steve Meier
• gEDA-dev: topological routing path search algorithms   Steve Meier
• gEDA-dev: New diagram (attempt at UML)   Steve Meier
• gEDA-dev: New diagram (attempt at UML)   Steve Meier
• gEDA-dev: New diagram (attempt at UML)   Steve Meier
• gEDA-dev: New diagram (attempt at UML)   Steve Meier
• gEDA-dev: New diagram (attempt at UML)   Steve Meier
• gEDA-dev: New diagram (attempt at UML)   Steve Meier
• gEDA-dev: New diagram (attempt at UML)   Steve Meier
• gEDA-dev: New diagram (attempt at UML)   Steve Meier
• gEDA-dev: New diagram (attempt at UML)   Steve Meier
• Hidden Nets Re: gEDA-dev: New diagram (attempt at UML)   Steve Meier
• gEDA-dev: New diagram (attempt at UML)   Steve Meier
• gEDA-dev: New diagram (attempt at UML)   Steve Meier
• gEDA-dev: Noscreen branch   Steve Meier
• gEDA-dev: google SOC   Timothy Normand Miller
• gEDA-dev: Google summer of code   Timothy Normand Miller
• Icarus Verilog projects in academic; was Re: gEDA-dev: Google summer of code   Timothy Normand Miller
• Icarus Verilog projects in academic; was Re: gEDA-dev: Google summer of code   Timothy Normand Miller
• gEDA-dev: EDIF docs?   Timothy Normand Miller
• gEDA-dev: Peripheral SoC Project ideas   Marc Moreau
• gEDA-dev: PCB - XY values of centrioid in BOM/DXF exproter (wasgEDA-user: PCB Element for a Molex 71661-2068?)   Gabriel Paubert
• Icarus Verilog projects in academic; was Re: gEDA-dev: Google summer of code   Aanjhan R
• gEDA-dev: Google SoC Announcement   Aanjhan R
• gEDA-dev: Google SOC suggestion for students   Aanjhan R
• gEDA-dev: proposed changes to drag on PCB   David Rowe
• gEDA-dev: proposed changes to drag on PCB   David Rowe
• gEDA-dev: Noscreen branch   David Rowe
• gEDA-dev: proposed changes to drag on PCB   David Rowe
• gEDA-dev: proposed changes to drag on PCB   David Rowe
• gEDA-dev: proposed changes to drag on PCB   David Rowe
• gEDA-dev: Revised symbol license text   David SMITH
• gEDA-dev: SoC Hopeful   Bob Sherbert
• gEDA-dev: SoC Hopeful   Bob Sherbert
• gEDA-dev: SoC Hopeful   Bob Sherbert
• gEDA-dev: Patch for "click on focus for zoom" bug   Tomaz Solc
• gEDA-dev: GPL clarification text -- please review & comment/flame!   Aapo Tahkola
• gEDA-dev: Hi... question about refdes_renum   C P Tarun
• gEDA-dev: Hi... question about refdes_renum   C P Tarun
• gEDA-dev: Hi... question about refdes_renum   C P Tarun
• gEDA-dev: Hi... question about refdes_renum   C P Tarun
• gEDA-dev: Hi... question about refdes_renum   C P Tarun
• gEDA-dev: GPL clarification text -- please review & comment/flame!   C P Tarun
• gEDA-dev: GPL clarification text -- please review & comment/flame!   C P Tarun
• gEDA-dev: GPL clarification text -- please review & comment/flame!   C P Tarun
• gEDA-dev: Revised symbol license text   C P Tarun
• gEDA-dev: SoC Hopeful   C P Tarun
• gEDA-dev: SoC Hopeful   C P Tarun
• gEDA-dev: SoC Hopeful   C P Tarun
• gEDA-dev: SoC Hopeful   C P Tarun
• gEDA-dev: SoC Hopeful   C P Tarun
• gEDA-dev: VHDL Interchange   Sandy Thom
• gEDA-dev: PCB - XY values of centrioid in BOM/DXF exproter (was gEDA-user: PCB Element for a Molex 71661-2068?)   Bert Timmerman
• gEDA-dev: PCB - XY values of centrioid in BOM/DXF exproter (wasgEDA-user: PCB Element for a Molex 71661-2068?)   Timmerman, Bert
• gEDA-dev: PCB - XY values of centrioid in BOM/DXF exproter(was gEDA-user: PCB Element for a Molex 71661-2068?)   Timmerman, Bert
• gEDA-dev: PCB - XY values of centrioid in BOM/DXF exproter (wasgEDA-user: PCB Element for a Molex 71661-2068?)   Timmerman, Bert
• gEDA-dev: Souce Contreol of big architectural projects in GoogleSoC....   Timmerman, Bert
• gEDA-dev: Souce Contreol of big architectural projects inGoogleSoC....   Bert Timmerman
• gEDA-dev: GPL clarification text -- please review & comment/flame!   Timmerman, Bert
• gEDA-dev: SoC Hopeful   Timmerman, Bert
• gEDA-dev: Souce Contreol of big architectural projects   Timmerman, Bert
• gEDA-dev: SoC: Gerber, DRC, gsch2pcb and D-BUS   Timmerman, Bert
• gEDA-dev: Revised symbol license text   Timmerman, Bert
• gEDA-dev: Revised symbol license text   Timmerman, Bert
• gEDA-dev: Verilog: $fscanf and $sscanf don't correctly report match count   Roger Williams
• gEDA-dev: Re: Icarus Verilog and Xilinx unisim files   Stephen Williams
• gEDA-dev: Re: Google summer of code   Stephen Williams
• gEDA-dev: Re: Google summer of code   Stephen Williams
• gEDA-dev: Re: Icarus Verilog Graffiti; was Re: Re: Google summer of code   Stephen Williams
• gEDA-dev: Re: Icarus Verilog projects in academic; was Re: Google summer of code   Stephen Williams
• gEDA-dev: Re: Icarus Verilog and Xilinx unisim files   Stephen Williams
• gEDA-dev: Re: VHDL, was Re: Hierarchical buses   Stephen Williams
• gEDA-dev: Re: VHDL, was Re: Hierarchical buses   Stephen Williams
• gEDA-dev: Re: VHDL, was Re: Hierarchical buses   Stephen Williams
• gEDA-dev: Re: VHDL, was Re: Hierarchical buses   Stephen Williams
• gEDA-dev: Re: VHDL, was Re: Hierarchical buses   Stephen Williams
• gEDA-dev: Re: VHDL as a file format   Stephen Williams
• gEDA-dev: Re: Verilog: $fscanf and $sscanf don't correctly report match count   Stephen Williams
• gEDA-dev: Re: Regarding SoC application   Stephen Williams
• gEDA-dev: Re: EDIF docs?   Stephen Williams
• gEDA-dev: Bug reports for gattrib   Stephen Williams
• gEDA-dev: Google summer of code   al davis
• gEDA-dev: Google SoC Announcement   al davis
• gEDA-dev: GPL clarification text -- please review & comment/flame!   al davis
• gEDA-dev: GPL clarification text -- please review & comment/flame!   al davis
• VHDL, was Re: gEDA-dev: Hierarchical buses   al davis
• VHDL, was Re: gEDA-dev: Hierarchical buses   al davis
• VHDL, was Re: gEDA-dev: Hierarchical buses   al davis
• gEDA-dev: gnetman inspired libgeda datastructures   al davis
• VHDL, was Re: gEDA-dev: Hierarchical buses   al davis
• gEDA-dev: Re: VHDL as a file format   al davis
• VHDL, was Re: gEDA-dev: Hierarchical buses   al davis
• gEDA-dev: Re: VHDL as a file format   al davis
• VHDL, was Re: gEDA-dev: Hierarchical buses   al davis
• gEDA-dev: Re: VHDL, was Re: Hierarchical buses   al davis
• VHDL, was Re: gEDA-dev: Hierarchical buses   al davis
• gEDA-dev: Re: VHDL, was Re: Hierarchical buses   al davis
• gEDA-dev: Re: VHDL, was Re: Hierarchical buses   al davis
• gEDA-dev: Re: VHDL, was Re: Hierarchical buses   al davis
• gEDA-dev: Re: VHDL, was Re: Hierarchical buses   al davis
• gEDA-dev: Re: VHDL, was Re: Hierarchical buses   al davis
• gEDA-dev: SoC: Gerber, DRC, gsch2pcb and D-BUS   al davis
• gEDA-dev: SoC: Gerber, DRC, gsch2pcb and D-BUS   al davis
• gEDA-dev: Re: VHDL as a file format   al davis
• gEDA-dev: SoC: Gerber, DRC, gsch2pcb and D-BUS   al davis
• gEDA-dev: Re: VHDL as a file format   al davis
• gEDA-dev: SoC: Gerber, DRC, gsch2pcb and D-BUS   al davis
• gEDA-dev: SoC: Gerber, DRC, gsch2pcb and D-BUS   al davis
• gEDA-dev: SoC: Gerber, DRC, gsch2pcb and D-BUS   al davis
• gEDA-dev: SoC: Gerber, DRC, gsch2pcb and D-BUS   al davis
• gEDA-dev: Regarding SoC application   al davis
• gEDA-dev: Regarding SoC application   al davis
• gEDA-dev: Regarding SoC application   al davis
• gEDA-dev: Regarding SoC application   al davis
• gEDA-dev: Re: Regarding SoC application   al davis
• gEDA-dev: SoC: Gerber, DRC, gsch2pcb and D-BUS   al davis
• gEDA-dev: Help in apply SoC2007   al davis
• gEDA-dev: New gnucap development snapshot 2007-03-29   al davis
• gEDA-dev: New member   klogus at email.it
• gEDA-dev: Re: VHDL as a file format   Stephen Brickles using shaun

Last message date: Sat Mar 31 21:51:18 EDT 2007
Archived on: Tue Apr 3 17:05:43 EDT 2007

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