gEDA-dev: SoC: Gerber, DRC, gsch2pcb and D-BUS

[Svenn Are Bjerkem]

On 3/23/07, al davis <ad136 at freeelectron.net> wrote:
> On Thursday 22 March 2007 23:02, DJ Delorie wrote:
> > Maybe I'm biased, but I disagree ;-)
>
> I understand that, but the link between schematic and simulation
> now is essentially nonfunctional. Having a translator that
> works and is complete opens up new capability way beyond what
> we have now.
>
> PCB and gschem both work, and do a good job, until you see how
> the whole system fits together.
>
> NGspice and gnucap also both work, but the translation only
> supports part of what is common to both, a little of the extra
> capability of ngspice, none of the extra capability gnucap has
> now, and none of the extra capability gnucap will have soon.
> That's why people stick to PSpice and LT-spice.

I am not so much afraid of people sticking to pspice and ltspice. I
would like to have a pleasant design flow not too dependant on make.
Qucs is now in 0.0.11, has the schematics, the simulator, the waveform
viewer, the integration. It doesn't have the pcb, the chip layouter
etc. But it is as free as the gEDA tools. If the HID version of pcb is
so HIDen, then why not use SOC to give qucs a pcb tab next to that
schematic tab and the waveform viewer tab. This environment would also
be perfect for Al's initiative to use vhdl as a file format. Qucs use
FreeVHDL. Each tool would know what architectures it can read, It
would be no problem for the microstrip guys to use the qucs simulator,
all other could plug in Al's Gnucap and the waveform viewer wouldn't
know the difference.

I think you are on the wrong list with your ideas, Al, you are too
many lightyears ahead.
-- 
Svenn