VHDL, was Re: gEDA-dev: Hierarchical buses

[Peter Clifton]

On Tue, 2007-03-20 at 19:02 -0400, al davis wrote:
> On Tuesday 20 March 2007 18:06, John Griessen wrote:
> > Al Davis proposed basing the gschem and gnetlist file formats
> > on VHDL.  I"m rusty on VHDL and like verilog, but it's the
> > same idea almost -- prepare for simulation by having the
> > netlist be a language  that defines a circuit for multiple
> > purposes -- circuit layout, circuit simulation, 3D system
> > design...
>
> I have been thinking about this, in more detail.  I am now 
> convinced that this is the only sensible way to go.  VHDL has 
> all of the features we need, and is a published standard.  
> Originally, I thought we would need to make small extensions.  
> I now believe we can use it without extensions, other than a 
> library written in VHDL.
> 
> People think of VHDL as a behavioral modeling language.  They 
> forget that it is a "Hardware Description Language" that can 
> represent structure.  This is the part that is most useful, and 
> the part that allows it to be able to describe anything that is 
> a composition of parts, each with attributes and connections.

Peter Brett and myself were looking at internal data-structure
representations, rather than file-formats. Indeed, we believe it should
be possible to read and write the existing format with internal data
structures similar to those in the diagram we presented earlier.

Presumably any tool which reads VHDL has to build its own internal
data-structures too. What do those tend to look like? I presume we can
make an internal data structure which can support many different netlist
and entity file formats.

Regards,

-- 
Peter Clifton

Electrical Engineering Division,
Engineering Department,
University of Cambridge,
9, JJ Thomson Avenue,
Cambridge
CB3 0FA

Tel: +44 (0)7729 980173 - (No signal in the lab!)