gEDA-dev: Hierarchical buses

[Peter Clifton]

One thing missing from the diagram posted earlier is a strategy for
buses.

I'm of the opinion that buses should be arbitrarily hierarchical. I'd
imagine buses being interchangeable with nets, with a net being the
smallest "atom" of connection.

The best use case I thought of for this feature would be LVDS pairs. Say
we want a bus of (say) 5 LVDS signals, each signal being a bus of two
nets. This allows information available at the design stage to be
incorporated into the data-structure. This could allow back / forward
probing with PCB to identify paired and bus-grouped signals.

Another possible application might be in a wiring harness deisgn with
multiple bundled multi-core cables.

How do we define the bus-pin in these cases?

Any thoughts anyone - either in usage or technical details?

Regards,

-- 
Peter Clifton

Electrical Engineering Division,
Engineering Department,
University of Cambridge,
9, JJ Thomson Avenue,
Cambridge
CB3 0FA

Tel: +44 (0)7729 980173 - (No signal in the lab!)