gEDA-dev: Re: Icarus Verilog and Xilinx unisim files

[Uwe Bonnes]

>>>>> "Stephen" == Stephen Williams <steve at icarus.com> writes:

    Stephen> Uwe Bonnes wrote:
    >> Dear Stephen,
    >> 
    >> thanks for the fixes for my recent reports. Now I want to run the top
    >> level of my design that instantiates a block ram. This hits another
    >> assertion.
    >> 
    >>> iverilog -o /tmp/a.out RAMB16_S9_S36.v ../glbl.v
    >> ivl: eval_expr.c:1660: draw_select_signal: Assertion `0' failed.  sh:
    >> line 1: 32620 Done /usr/local/lib/ivl/ivlpp -L -F/tmp/ivrlg2e76bb53
    >> -f/tmp/ivrlge76bb53 32621 Abgebrochen | /usr/local/lib/ivl/ivl
    >> -C/tmp/ivrlhe76bb53 -C/usr/local/lib/ivl/vvp.conf -- -
    >> 
    >> Are you interested in those kind of reports too? Should they be
    >> checked into the bug database?
    >> 
    >> You can get access to the Xilinx unisim file by downloading Xilinx
    >> ISE Webpack for free. I guess however, you already have access to
    >> ISE.

    Stephen> I do want those types of bug reports, and I do use Xilinx
    Stephen> unisim libraries in my day job regularly. Note that they are
    Stephen> sometimes a moving target (they change from ise version to
    Stephen> version).

The problem with the RAMB16_S9_S36.v file probably boils down to the problem
with Verilog 2001 Vector part selects (see also Bug 1675789). By giving the
define "-Dlegacy_model", a non-Verilog-2001 model is used for the Block RAM
and I can run my testbench. 

Cheers
-- 
Uwe Bonnes                bon at elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
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