gEDA-dev: Re: Icarus Verilog and Xilinx unisim files

[Stephen Williams]

Uwe Bonnes wrote:
>>>>>> "Stephen" == Stephen Williams <steve at icarus.com> writes:
> 
> 
>     Stephen> If you're building from source, one easy thing you can do is
>     Stephen> see the assert in eval_expr.c line 1660 and replace it with an
>     Stephen> ivl_assert that will give a Verilog file/line number as
>     Stephen> well. That may help you narrow down the problem. But if you
>     Stephen> can't, that's OK to. Just make sure I have the version
>     Stephen> information I need.
> 
> It's not that easy.
> 
> eval_expr.c is inside the tgt-vvp directory and  compiled with gcc, while
> ivl_assert uses C++ constructs. 
> 
> I have noe ideas, what arguments ivl_asserts() expects in the context of
> eval_expr.c
> 

Ah, ivl_assert would not work in and of the code generators.
Unfortunately, the line number information is lost by the time it
gets to the code generators.

-- 
Steve Williams                "The woods are lovely, dark and deep.
steve at icarus.com           But I have promises to keep,
http://www.icarus.com         and lines to code before I sleep,
http://www.picturel.com       And lines to code before I sleep."