gEDA-dev: Another Verilog test

[Stephen Brickles using shaun]

verilog pr1636409.v 

Tool:	VERILOG-XL	05.70.001-p   Jan 23, 2007  15:08:53

Copyright (c) 1995-2004 Cadence Design Systems, Inc.  All Rights Reserved.
Unpublished -- rights reserved under the copyright laws of the United States.

Copyright (c) 1995-2004 UNIX Systems Laboratories, Inc.  Reproduced with 
Permission.

THIS SOFTWARE AND ON-LINE DOCUMENTATION CONTAIN CONFIDENTIAL INFORMATION
AND TRADE SECRETS OF CADENCE DESIGN SYSTEMS, INC.  USE, DISCLOSURE, OR
REPRODUCTION IS PROHIBITED WITHOUT THE PRIOR EXPRESS WRITTEN PERMISSION OF
CADENCE DESIGN SYSTEMS, INC.
RESTRICTED RIGHTS LEGEND

Use, duplication, or disclosure by the Government is subject to
restrictions as set forth in subparagraph (c)(1)(ii) of the Rights in
Technical Data and Computer Software clause at DFARS 252.227-7013 or
subparagraphs (c)(1) and (2) of Commercial Computer Software -- Restricted
Rights at 48 CFR 52.227-19, as applicable.

                Cadence Design Systems, Inc.
                555 River Oaks Parkway
                San Jose, California  95134

For technical assistance please contact the Cadence Response Center at
1-877-CDS-4911 or send email to support at cadence.com

For more information on Cadence's Verilog-XL product line send email to
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Compiling source file "pr1636409.v"
Highest level modules:
top

fail=x0x0, good=x0x0, en=0 at 1
fail=0000, good=0000, en=0 at 2
fail=0000, good=0000, en=1 at 11
fail=0101, good=0101, en=1 at 12
fail=1010, good=1010, en=0 at 31
fail=0000, good=0000, en=0 at 32
L31 "pr1636409.v": $finish at simulation time 50
0 simulation events (use +profile or +listcounts option to count)
CPU time: 0.1 secs to compile + 0.0 secs to link + 0.1 secs in simulation
End of Tool:	VERILOG-XL	05.70.001-p   Jan 23, 2007  15:08:56


ncverilog pr1636409.v 

ncverilog: 05.70-s001: (c) Copyright 1995-2006 Cadence Design Systems, Inc.
file: pr1636409.v
	module worklib.top:v
		errors: 0, warnings: 0
		Caching library 'worklib' ....... Done
	Elaborating the design hierarchy:
	Building instance overlay tables: .................... Done
	Generating native compiled code:
		worklib.top:v <0x6e7a3dc7>
			streams:   7, words:   681
	Loading native compiled code:     .................... Done
	Building instance specific data structures.
	Design hierarchy summary:
		            Instances  Unique
		Modules:            1       1
		Registers:          4       4
		Scalar wires:       1       -
		Vectored wires:     2       -
		Always blocks:      3       3
		Initial blocks:     1       1
		Cont. assignments:  2       3
	Writing initial simulation snapshot: worklib.top:v
Loading snapshot worklib.top:v .................... Done
ncsim> source ./.bin/ius/tools/inca/files/ncsimrc
ncsim> run

Warning!  some objects excluded from $dumpvars due to access restrictions, use 
+access+r on command line for access to all objects
            File: ./pr1636409.v, line = 26, pos = 12
           Scope: top
            Time: 0 FS + 0

fail=x0x0, good=x0x0, en=0 at 1
fail=0000, good=0000, en=0 at 2
fail=0000, good=0000, en=1 at 11
fail=0101, good=0101, en=1 at 12
fail=1010, good=1010, en=0 at 31
fail=0000, good=0000, en=0 at 32
Simulation complete via $finish(1) at time 50 NS + 0
./pr1636409.v:31     #50 $finish;
ncsim> exit


vcs pr1636409.v 

*** Using loader /usr/ccs/bin/ld instead of cc ...
                         Chronologic VCS (TM)
            Version Y-2006.06 -- Tue Jan 23 15:09:48 2007
               Copyright (c) 1991-2006 by Synopsys Inc.
                         ALL RIGHTS RESERVED

This program is proprietary and confidential information of Synopsys Inc.
and may be used and disclosed only as authorized in a license agreement
controlling such use and disclosure.

Parsing design file 'pr1636409.v'
Top Level Modules:
       top
No TimeScale specified
Starting vcs inline pass...
1 module and 0 UDP read.
recompiling module top
if [ -x ../simv ]; then chmod -x ../simv; fi
/usr/ccs/bin/ld  -o ../simv  /apps/vcs/vcs/sparcOS5/lib/crt1.o 
/apps/vcs/vcs/sparcOS5/lib/crti.o  5NrI_d.o 5NrIB_d.o N654_1_d.o SIM_l.o  
/apps/vcs/vcs/sparcOS5/lib/libvirsim.a -lnsl -lsocket -ldl     
/apps/vcs/vcs/sparcOS5/lib/libvcsnew.so     -lm -lc  -ldl  
/apps/vcs/vcs/sparcOS5/lib/crtn.o   
../simv up to date
CPU time: 2 seconds to compile + 0 seconds to link

simv

Chronologic VCS simulator copyright 1991-2005
Contains Synopsys proprietary information.
Compiler version Y-2006.06; Runtime version Y-2006.06;  Jan 23 15:10 2007

fail=0000, good=0000, en=0 at 1
fail=0000, good=0000, en=1 at 11
fail=0101, good=0101, en=1 at 12
fail=0000, good=0000, en=0 at 31
$finish at simulation time                   50
           V C S   S i m u l a t i o n   R e p o r t 
Time: 50
CPU Time:      0.430 seconds;       Data structure size:   0.0Mb
Tue Jan 23 15:10:01 2007

Stephen