gEDA-dev: Another Verilog test

[Stephen Williams]

This sample program is from problem report 1636409 in the iverilog
bugs database. This one has shown itself to be somewhat tricky. It
appears to actually have a race condition of sorts. It's a ternary
with a 1unit delay, and multiple of its inputs are changing at 1unit
delays. Icarus Verilog does the wrong thing, but I'd like to see
some big names do something with this to get a better grip on what
is really happening.

-- 
Steve Williams                "The woods are lovely, dark and deep.
steve at icarus.com           But I have promises to keep,
http://www.icarus.com         and lines to code before I sleep,
http://www.picturel.com       And lines to code before I sleep."
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/* pr1636409 */
module top;
  wire [3:0] fail, good;
  wire eni;
  reg [2:0] rg;
  reg in, en, clk;

  assign #1 eni = en;
  assign #1 fail = (eni) ? {rg,in} : 'b0;
  assign #1 good = {4{eni}} & {rg,in};

  always @(fail or good or eni) begin
    $strobe("fail=%b, good=%b, en=%b at %0t", fail, good, eni, $time);
  end

  always #10 clk = ~clk;

   always @(posedge clk) begin
     en = ~en;
     in = ~in;
     rg = ~rg;
   end

  initial begin
    $dumpfile("results.vcd");
    $dumpvars(0, top);
    clk = 0;
    en = 0;
    in = 0;
    rg = 3'b101;
    #50 $finish;
  end
endmodule