gEDA-dev: Re: verilog operator precedence question: logical & and reduction |

[Stephen Williams]

Stephan Boettcher wrote:
> Hello Stephen,
> 
> Here is another contruct that our compiler barfs on:
> 
>    input      Tclk;
>    output     out;
>    reg [35:0] Vsel;
>    reg [35:0] bits;
> 
>    assign     out = |(bits & Vsel) & Tclk;
> 
> and in this case it may have a point.
> 
> In Lee: Verilog Quickstart, 2nd Edition, page 80, the operator
> precedence table does not list the reduction operators seperately.

Yeah, the Quickstart is a good book for getting started, but is
not good for getting answers to subtle behavior questions. It is
ultimately the standard that I use for resolving those questions
so I can't really point to a book that does it well.

> That could be read that the bitwise & has higher precedence than
> the reduction |.  Iverilog treats the reduction operator with higher
> precedence than the bitwise operator.

Unary operators always have higher priority then binary operators.

> OTOH, writing it in the reverse order should be unambiguous:
> 
>   assign out = Tclk & |(bits & Vsel);

This should be the same as your above example. It has the benefit
that humans are less confused by it too.

> What do the relevant standards have to say about this?

They say that unary operators have higher precedence then binary
operators.


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