gEDA-dev: verilog operator precedence question: logical & and reduction |

[Evan Lavelle]

Stephan Boettcher wrote:
> Hello Stephen,
> 
> Here is another contruct that our compiler barfs on:
> 
>    input      Tclk;
>    output     out;
>    reg [35:0] Vsel;
>    reg [35:0] bits;
> 
>    assign     out = |(bits & Vsel) & Tclk;
> 
> and in this case it may have a point.
> 
> In Lee: Verilog Quickstart, 2nd Edition, page 80, the operator
> precedence table does not list the reduction operators seperately.
> 
> That could be read that the bitwise & has higher precedence than
> the reduction |.  Iverilog treats the reduction operator with higher
> precedence than the bitwise operator.
> 
> OTOH, writing it in the reverse order should be unambiguous:
> 
>   assign out = Tclk & |(bits & Vsel);
> 
> What do the relevant standards have to say about this?

The text of the standards (both 95 and 2001) is unclear, which isn't
unusual. However, the expression syntax on p730 of the 2001 LRM clearly
shows that all unary operators have higher precedence than any binary
operator. I think this is pretty much universal in other languages.

What's your compiler? Does it actually give an error?

Evan