gEDA-dev: Re: Icarus verilog question

[Anthony J Bybell]

On Sun, 21 Jan 2007, Stephen Williams wrote:

> Arrays of reals are not supported in Verilog, but *I* intend to support
> them. So any array support you add should include support for reals.

OK, no problem--I'm of the mindset that the standard isn't written in
stone and you never know when that kind of thing would be supported in
the future.  BTW, does Verilog support multi-dimensional arrays?  I
haven't looked at the grammar in a while.


> laying out memories would be utterly useless. I can think of two ways:
> Treat arrays like scopes, and allow the user to select words to display,
> or simply treat array words like any other displayable item. Mostly
> the issue here would be the signal browser and not the display.

OK, I see where you're coming from.  I'll put on my thinking hat.  IIRC,
the GHW format supports arrays so I should probably look at what Tristan
did for that.  My guess is he exploded them down into a separate
hierarchy.  (i.e., x[2][7:0] would be have [0] and [1] scalar sigs present
one level down from x)

Whatever the case, adding array support to VCD doesn't sound like the most
portable thing (unless it's been specified already by some vendor or
committee) so I'm wondering if it would best be done with an auxiliary
adata file.  *shrugs*

LXT (but not LXT2 or VZT) currently has implemented the ability to specify
array rows during signal creation and value change writing and it "should"
work but I will have to re-tool the loader slightly in order to process
them and likely QA the writer.  I'll look into all of this in the very
near future.

-Tony