gEDA-dev: Re: Icarus verilog question

[Stephen Williams]

Andrew Lentvorski wrote:
> Steven Wilson wrote:
>> I've never seen a dump list with memories included. 
> 
> Okay.  Well, I'd at least like to have the option.  So, I'll file that
> as an enhancement request.
> 
>> The format is really only designed to dump "vectors."
> 
> But, rf[0] *is* a vector.  I can understand not dumping it by default,
> but if I explicitly list it, I really want it.

That's beyond the scope of the standard, but it is a reasonable
request and probably not very hard to implement. Do file it as an
enhancement request.

> In addition, why won't rf[0] show up when I put it in a $monitor statement?

That would be a bug. File a bug report. Bug reports that have
clear and simple (and complete!) sample programs get fixed
fastest.

> Finally, how do I grab a slice of rf[0] aka rf[0][15:12] ?  Do I have to
> wire *that* out and then slice the wire?  I'm probably going to have to
> build a parameterized register file module if I want
> rf[someWire[2:0]][15:12]?  This is nuts.

That should work. You can take bit/part selects of array words.

> Why do register arrays not behave like an array of registers?  Is this
> in the standard somewhere or is everybody just following bugs in
> Verilog-XL?

In 1995 there were no arrays. "Memories" are special things that
were not quite the same as arrays. V2001 tries to generalize the
memory into arrays, allowing for a more orthogonal treatment of
the concepts. But some limits still remain.


-- 
Steve Williams                "The woods are lovely, dark and deep.
steve at icarus.com           But I have promises to keep,
http://www.icarus.com         and lines to code before I sleep,
http://www.picturel.com       And lines to code before I sleep."