gEDA-dev: Icarus verilog question

[Steven Wilson]

Andrew - I'm don't have most of the answers for you -but I'll just
relate the answer I got back a few years ago from Cadence when I found a
place where XL didn't follow the standard.  They said something to the
effect of "Well - the standards folks just didn't understand the flavor
of how XL worked." So - from their point of view, XL didn't have any
bugs ;-)

Can't tell you about $monitor not dumping rf[0] - Would Mr. Williams
care to reply?  Steve knows the spec far better than I do at this point
(having implemented same.)

Steve Wilson

Andrew Lentvorski wrote:
> Steven Wilson wrote:
>> I've never seen a dump list with memories included. 
>
> Okay.  Well, I'd at least like to have the option.  So, I'll file that
> as an enhancement request.
>
>> The format is really only designed to dump "vectors."
>
> But, rf[0] *is* a vector.  I can understand not dumping it by default,
> but if I explicitly list it, I really want it.
>
> In addition, why won't rf[0] show up when I put it in a $monitor
> statement?
>
> Finally, how do I grab a slice of rf[0] aka rf[0][15:12] ?  Do I have
> to wire *that* out and then slice the wire?  I'm probably going to
> have to build a parameterized register file module if I want
> rf[someWire[2:0]][15:12]?  This is nuts.
>
> Why do register arrays not behave like an array of registers?  Is this
> in the standard somewhere or is everybody just following bugs in
> Verilog-XL?
>
> -a
>
>
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