gEDA-dev: Need a Verilog test run

[Stephen Brickles using shaun]

Output from ncverilog :

ncverilog: 05.70-s001: (c) Copyright 1995-2006 Cadence Design Systems, Inc.
...
file: test.v
	module worklib.test:v
		errors: 0, warnings: 0
...
ncsim> run
At 1 value is 0000000000
At 2 value is 00000xxxxx
At 3 value is 1111111111
At 4 value is 00000xxxxx
At 5 value is 0000000000
At 6 value is 00xxxxxxxx
Simulation complete via $finish(1) at time 7 NS + 0
./test.v:13     $finish;
ncsim> exit