gEDA-dev: iverilog and Xilinx 8.2

[Stephen Williams]

A couple things:

1) You don't want the "-tfpga" flag on your command line. That is
for synthesis, but you are trying to simulate.

2) This looks like a problem long since fixed. Version?

3) Your command line is intimidatingly long. You can and should
use a command file. See this url:

   <http:/iverilog.wikia.com/Command_File_Format>

4) Isn't this post better suited to the geda-user list?

Daniel O'Connor wrote:
> Hi,
> 
> I'm trying to use iverilog to simulate my design to try and avoid using
> the piggish project navigator as much as possible however I am having
> trouble with the Xilinx primitives, eg..
> 
> [inchoate 21:52] ~/work/fpga/SA > iverilog -y . -y $XILINX/verilog/src/unisims -y $XILINX/verilog/src/XilinxCoreLib -tfpga SA_test2.v
> /usr/local/Xilinx/verilog/src/unisims/DCM.v:45: syntax error
> /usr/local/Xilinx/verilog/src/unisims/DCM.v:45: error: syntax error in parameter list.
> /usr/local/Xilinx/verilog/src/unisims/DCM.v:46: syntax error
> /usr/local/Xilinx/verilog/src/unisims/DCM.v:46: error: syntax error in parameter list.
> /usr/local/Xilinx/verilog/src/unisims/DCM.v:47: syntax error
> /usr/local/Xilinx/verilog/src/unisims/DCM.v:47: error: syntax error in parameter list.
> /usr/local/Xilinx/verilog/src/unisims/DCM.v:49: syntax error
> /usr/local/Xilinx/verilog/src/unisims/DCM.v:49: error: syntax error in parameter list.


-- 
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