gEDA-dev: iverilog and xilinx xc4000 problem

[Chris H]

Just a guess. did you try using a non-blocking assignment ?

//always @(posedge Clock or posedge Clear) Qout = Clear ? 0 : (Load ? Qin : 
Qout + 1);
always @(posedge Clock or posedge Clear) Qout <= Clear ? 0 : (Load ? Qin : 
Qout + 1);

Chris

>From: Rich Cummings <cumminr at yahoo.com>
>Reply-To: gEDA developer mailing list <geda-dev at moria.seul.org>
>To: geda-dev at moria.seul.org
>Subject: gEDA-dev: iverilog and xilinx xc4000 problem
>Date: Sun, 12 Aug 2007 11:37:34 -0700 (PDT)
>
>Hello,
>
>Any help is greatly appreciated. Why am I getting this error?
>Assertion failed: 0, file t-xnf.cc, line 436
>
>I'm trying to synthesize the below verilog code using this command line:
>iverilog -pncf=myfirst.ncf -txnf -ppart=XC4005XL-3pc84 Counter10BitUp.v 
>-omyfirst.xnf
>
>Looking in the iverilog source code, it appears that draw_carry() is being 
>called with an adder_type of FORCE0. So I guess this means it doesn't like 
>the "Qout+1" in the code below.
>
>Is my command wrong? Do I have to wait for iverilog to support "-t fpga" 
>for xc4000? Should I just buck up and spend some money on a modern fpga?
>
>Any help is appreciated. Thanks in advance.
>
>/////////////////////////////////////////////////////////////////////////////////////////
>iverilog version: Icarus Verilog version 0.8.4 ($Name: v0_8_4 $)
>hardware:        XESS XS40 v1.4 - w/ Xilinx XC4005XL-PC84
>
>/////////////////////////////////////////////////////////////////////////////////////////
>// My 10 bit Up Counter - w/ Load
>module Counter_10Bit_Up ( Qout, Qin, Load, Clear, Clock );
>     output [9:0]  Qout;
>     input  [9:0]  Qin;
>     input         Clear;
>     input         Clock;
>     input         Load;
>     reg    [9:0]  Qout;
>
>     always @(posedge Clock or posedge Clear) Qout = Clear ? 0 : (Load ? 
>Qin : Qout + 1);
>
>endmodule
>
>module xr4005xl_counter ( qout, qin, load, clr, clk );
>     output [9:0]  qout;
>     input  [9:0]  qin;
>     input         load;
>     input         clr;
>     input         clk;
>
>     wire   [9:0]  qin;
>     wire          load;
>     wire          clr;
>     wire          clk;
>
>     Counter_10Bit_Up dut ( qout, qin, load, clr, clk );
>
>     $attribute( qout , "OPAD", "0,0,0,0,0,0,0,0,0,0" );
>     $attribute( qin ,  "IPAD", "0,0,0,0,0,0,0,0,0,0" );
>     $attribute( load , "IPAD", "0" );
>     $attribute( clr  , "IPAD", "0" );
>     $attribute( clk  , "IPAD", "0" );
>endmodule
>
>


>
>
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