gEDA-dev: verilog-AMS

[Kev Cameron]

Stephen Brickles using shaun wrote:
>> but the digital logic part of the stuff being simulated is _much_ faster in
>> RTL than in transistor-spice.   Simulating each different part adequately is good.
>>     
>> john
>>     
>
> Agreed - Verilog is great for regular RTL digital simulations, but the
> discussion was about replacing the analog SPICE part of the mixed-signal
> simulation with Verilog-AMS - I just wanted to make sure that everyone knows
> that Verilog-AMS is not a magic replacement for regular SPICE compiled-in models
> in a simulator.  It is great for adding a model that your simulator doesn't
> support, but it will slow your simulation down.
>
> Stephen
>   
The advantage of Verilog-AMS over Spice is that the transistor model is 
not pre-compiled so the compiler can optimize each transistor instance. 
It should therefore be faster than a traditional SPICE simulation which 
has a limited set of precompiled models - if it isn't faster it's 
probably just a badly implemented.

Kev.


>
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