gEDA-dev: New diagram (attempt at UML)

[Svenn Are Bjerkem]

On 4/11/07, Dan McMahill <dan at mcmahill.net> wrote:
> John Doty wrote:
> >
> > On Apr 10, 2007, at 3:26 PM, Steve Meier wrote:
>
>
>
> > I think so. You don't want to try to lay out the innards of an IC on  a
> > PC board.
> >
> >> I should then also mark if
> >> the page has a physical realization (for PCB) or not (for simulation).
> >
> >
> > I think if it has a footprint, that's evidence that this is the level
> > that goes on a PC board. If it has a model, that's evidence that this
> > is the level where you use the model rather than the source for
> > simulation (if you have no model and no source, the symbol should
> > represent a simulation primitive like a resistor). But Svenn seems to
> > have more ambitious ideas: you might want to understand how Cadence
> > does it (don't ask me!).

Yes, my vision is to completely replace Cadence one day as front end
IC design tool. When that is fulfilled, I will go on to replace them
on the IC layout side. I just have to learn how to write software
first.

Problem is that you are not allowed to lose any time by using open
source tools. The migration must cost nothing and no time waste is
allowed. On the other side, so many hundreds of thousands of Euro paid
in license fees.... If all companies using cadence would donate 1% of
their license fee to open source development ... Dream on, dude.

Regards,
Svenn