gEDA-dev: VHDL Interchange

[al davis]

On Tuesday 03 April 2007 18:33, Peter Clifton wrote:
> On Tue, 2007-04-03 at 18:18 -0400, al davis wrote:
> > On Tuesday 03 April 2007 17:57, Peter Clifton wrote:
> > > Net-segments on schematics are not drawn with simulation
> > > in mind.
> >
> > Stop thinking Spice for simulation.
>
> I didn't say spice.
>
> How many schematics are drawn with the wires linking
> components having some meaningful physical representation.

The representation must preserve their placement and attributes  
even if it is not used for simulation.  That's why they must be 
entities.

How do you find the current through a signal?

To the simulator (or anyone else) .. Just because the 
information is there doesn't mean you have to use it.

> > That's what the alternative architectures are for.
>
> If you want to simulate a PCB layout, that is different, but
> traces != nets.

They are completely different architectures.

> > I am thinking that the translators could be designed as a
> > pair of gnucap language plugins, which will translate
> > syntax without changing content.  In some cases there would
> > be another that would generate alternate archtectures. 
> > It's looking pretty good, and easy.  We will see what
> > develops.
>
> This all sounds good, especially since gnucap is now designed
> to be so plug-able. libgeda certainly isn't plug-able in
> terms of its file-format. This isn't a cricicism per-se, but
> something which could be abstracted out further if so
> desired.

Other tools do not need to change in any way.  Part of the goal 
is to import foreign formats, which most certainly will not do 
anything to accomodate gnucap or gEDA.

I would like to go through the transition problems first with 
gnucap and stand-alone translators, then after the bugs are 
worked out offer it to everyone else.