gEDA-dev: VHDL Interchange

[Peter Clifton]

On Tue, 2007-04-03 at 18:18 -0400, al davis wrote:
> On Tuesday 03 April 2007 17:57, Peter Clifton wrote:
> > Net-segments on schematics are not drawn with simulation in
> > mind.
> 
> Stop thinking Spice for simulation.

I didn't say spice.

How many schematics are drawn with the wires linking components having
some meaningful physical representation.

Sure, you could assign them circuit parameters, like inductance,
coupling to other wires, but you'd still have to ensure the right
topology of their connection.

If you want to simulate from the schematic, you might as well use a
specific model for the wire, transmission line or whatever.

> That's what the alternative architectures are for.

If you want to simulate a PCB layout, that is different, but traces !=
nets.

[snip]

> I am thinking that the translators could be designed as a pair 
> of gnucap language plugins, which will translate syntax without 
> changing content.  In some cases there would be another that 
> would generate alternate archtectures.  It's looking pretty 
> good, and easy.  We will see what develops.

This all sounds good, especially since gnucap is now designed to be so
plug-able. libgeda certainly isn't plug-able in terms of its
file-format. This isn't a cricicism per-se, but something which could be
abstracted out further if so desired.

Peter