gEDA-dev: VHDL Interchange

[al davis]

On Tuesday 03 April 2007 17:57, Peter Clifton wrote:
> Net-segments on schematics are not drawn with simulation in
> mind.

Stop thinking Spice for simulation.

> I guess if you back-export from PCB, you can consider 
> traces as components which could be simulated, but there is
> no direct link between a schematic net (list of connections
> between circuit elements) and those traces.

That's what the alternative architectures are for.

There will also be an architecture for Spice, so the system will 
support ng-spice.  Gnucap doesn't need it.



> Shame.. I rather liked VHDL, but I guess they are equivalent
> in terms of their function.

Actually VHDL is better in this case, because 
entity/architecture is a language supported concept.

A while back, I commented on VHDL being "Hardware Description 
Language" and Verilog being a simulation and verification 
language.

That comment is not intended to be critical of either.  I have 
worked with people on both committees, and as a member of a 
Verilog-AMS committee.  The difference is true.  Ask them.  
They will tell you that.

Discussion with the VHDL people centered around hardware 
description.  They try to accomodate simulation, but it was 
clear that hardware description in general was first on their 
mind.  In contrast, in discussion with Verilog people it was 
clear that verification and simulation were first on their 
mind, with general hardware description a bit distant.

In this case, only the structural subset is used, and there is a 
direct mapping.

I am thinking that the translators could be designed as a pair 
of gnucap language plugins, which will translate syntax without 
changing content.  In some cases there would be another that 
would generate alternate archtectures.  It's looking pretty 
good, and easy.  We will see what develops.