gEDA-dev: VHDL Interchange

[Peter Clifton]

On Tue, 2007-04-03 at 17:30 -0400, al davis wrote:

> > Nets		---->		Intuitively I want to describe nets as
> > 				vhdl signals. It may be necessary to
> > 				describe a net as a design entity and
> > 				instantiate as a component.
> 
> No.  Nets are like components, so they can carry placement info.  
> The architecture for simulation is a direct connection between 
> ports.

Net-segments on schematics are not drawn with simulation in mind. I
guess if you back-export from PCB, you can consider traces as components
which could be simulated, but there is no direct link between a
schematic net (list of connections between circuit elements) and those
traces.

> The intent is a simple syntax translation.  Nothing more.
> 
> As I look at it more, it seems more likely to use Verilog than 
> VHDL.  I have had some discussions with Verilog people about 
> how to deal with the entity/architecture concept, and I have 
> some ideas.  Nothing final yet.

Shame.. I rather liked VHDL, but I guess they are equivalent in terms of
their function.

-- 
Peter Clifton

Electrical Engineering Division,
Engineering Department,
University of Cambridge,
9, JJ Thomson Avenue,
Cambridge
CB3 0FA

Tel: +44 (0)7729 980173 - (No signal in the lab!)