gEDA-dev: VHDL Interchange

[Peter Clifton]

On Wed, 2007-03-28 at 05:12 +0100, Sandy Thom wrote:
> Al,
> 
> I have been intrigued by your suggestions for a VHDL interchange format.
> The following is an attempt to convey the idea at a conceptual level for
> gschem schematics. I would really appreciate your guidance.
> 
> gschem				VHDL
> ------------------------------------------------------------------------
> Design* 	---->		Self contained top level entity with
> 				a structural architecture describing
> 				the interconnection of schematics.

I'm not sure we need to specify the interconnection of schematics - just
the "root" schematic - which could its-self pull in other blocks.

This act may build up a "design" structure internal to libgeda.
Depending on what you're doing though, you might want to export such a
notion.

> Schematic	---->		Entity with ports being electrical 
> 				connections to other schematics. Version
> 				number and other top level attributes
> 				expressed as vhdl attributes. 
> 				Structural architecture with component
> 				instantiations and interconnections. 

Actually, I'd call that a "circuit". A circuit doesn't have to have a
schematic, it could be VHDL specified, it could just be a black-box type
interface to something - e.g. a microprocessor chip, or an op-amp.

The only "Mports" (master ports) are those which this circuit makes
available to a higher level in the hierarchy, not connections to
sub-circuits _inside_ this circuit. (gnetman makes a similar distinction
of Mports and ports).

I consider a "schematic" as one possible way of defining (or
representing) the internals of a circuit. It isn't required though.

> Components	---->		Entity with ports being the terminals 
> 				of the device. Attributes expressed as
> 				vhdl attributes. Behavioural 
> 				architecture describing component for
> 				simulation.

This is just a "circuit", (interface definition), with no particular
schematic representation - it is a black box. It will likely have a
symbolic representation ("symbol") though.

> Symbols		---->		How to best describe the relationship
> 				between the component and its symbol? 

A "symbol" is like a "schematic", a graphical representation of a
"circuit", but doesn't contain enough information to define the internal
connections or working of the circuit. It is purely for human
convenience, and can be used to represent a "circuit" (component or
sub-circuit) in another schematic page.

> Nets		---->		Intuitively I want to describe nets as 
> 				vhdl signals. It may be necessary to 
> 				describe a net as a design entity and
> 				instantiate as a component.

I'd agree with "signals".

> * gschem does not yet use the concept of a design but I noticed that
> Peter Clifton suggested it in his musings on hierarchy.

Did you take a look at 
http://geda.seul.org/wiki/geda:data_structure_design_discussion

I added some explanations as to what I thought various terms mean. Its
not specifically geared to a VHDL interchange, but I'd hope to define
things in such a way that VHDL interchange is possible.


-- 
Peter Clifton

Electrical Engineering Division,
Engineering Department,
University of Cambridge,
9, JJ Thomson Avenue,
Cambridge
CB3 0FA

Tel: +44 (0)7729 980173 - (No signal in the lab!)