gEDA-dev: VHDL Interchange

[John Sheahan]

al davis wrote:
> On Wednesday 28 March 2007 00:12, Sandy Thom wrote:
>> Al,
>>
>> I have been intrigued by your suggestions for a VHDL
>> interchange format. The following is an attempt to convey the
>> idea at a conceptual level for gschem schematics. I would
>> really appreciate your guidance.
>>
>> gschem				VHDL
>> -------------------------------------------------------------
>> ----------- Design* 	---->		Self contained top level entity
>> with a structural architecture describing
>> 				the interconnection of schematics.
>>
>> Schematic	---->		Entity with ports being electrical
>> 				connections to other schematics. Version
>> 				number and other top level attributes
>> 				expressed as vhdl attributes.
>> 				Structural architecture with component
>> 				instantiations and interconnections.
> 
> Yes.

what is described here is a netlist.
A schematic also includes page layout information
(library symbol placement on sheet, perhaps symbol version, and physical 
placement of the interconnect lines on the sheet, as well as the logical 
interconnect between submodule ports.
John
> 
>> Components	---->		Entity with ports being the terminals
>> 				of the device. Attributes expressed as
>> 				vhdl attributes. Behavioural
>> 				architecture describing component for
>> 				simulation.
> 
> Yes.  The Behavioural architecture is supplied by a separate 
> library, so it is not needed unless you want to simulate.
> 
>> Symbols		---->		How to best describe the relationship
>> 				between the component and its symbol?
> 
> Symbols are another architecture.
> 
>> Nets		---->		Intuitively I want to describe nets as
>> 				vhdl signals. It may be necessary to
>> 				describe a net as a design entity and
>> 				instantiate as a component.
> 
> No.  Nets are like components, so they can carry placement info.  
> The architecture for simulation is a direct connection between 
> ports.
> 
> 
> The intent is a simple syntax translation.  Nothing more.
> 
> As I look at it more, it seems more likely to use Verilog than 
> VHDL.  I have had some discussions with Verilog people about 
> how to deal with the entity/architecture concept, and I have 
> some ideas.  Nothing final yet.
> 
> I am thinking the translators could be written as gnucap 
> language plugins.  A common wrapper will use two language 
> plugins, one to read, one to write.  Just read and write.  Add 
> another hook to process, and it is a nice framework for general 
> translation.  The reason for having the intermediate format is 
> to allow multiple architectures to be stored together.
> 
> 
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