gEDA-dev: about gEDA hierarchical netlist

[Mike Jarabek]

On Sat, 2006-09-23 at 10:52 -0500, John Griessen wrote:
> I'd like to see that makefile.  Is it something you will share if I don't pester 
> you with questions about it?
> 

Yes, I will put together an example, and post it for all.  Give me a
couple of days to get it together.

> John G
> 
> Mike Jarabek wrote:
> > Hi,
> > 
> > On Sat, 2006-09-23 at 06:56 -0400, pt75234 at aim.com wrote:
>   The script also
> >> generates a report file for the entire hierarchy of the design.
> >>
> > 
> > I usually use a makefile that knows how to convert schematics to
> > verilog/vhdl with a rule.
> 
> 
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-- 
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                              Mike Jarabek        
                                FPGA/ASIC Designer
  http://www.istop.com/~mjarabek                    
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