gEDA-dev: about gEDA hierarchical netlist

[John Griessen]

I'd like to see that makefile.  Is it something you will share if I don't pester 
you with questions about it?

John G

Mike Jarabek wrote:
> Hi,
> 
> On Sat, 2006-09-23 at 06:56 -0400, pt75234 at aim.com wrote:
  The script also
>> generates a report file for the entire hierarchy of the design.
>>
> 
> I usually use a makefile that knows how to convert schematics to
> verilog/vhdl with a rule.