gEDA-dev: about gEDA hierarchical netlist

[pt75234 at aim.com]

Hi Everyone,
I am new to this posting. I've been trying to find out more about 
hierarchical Verilog/VHDL/Spice netlist features in gEDA. I searched 
and found some discussions on this topic from the geda-dev May 2006 
maillist archive regarding spice's hierarchical netlist. I had also 
tried to actually run some test examples to understand the hierarchical 
netlist feature in gEDA in general. Similar to what others had said in 
the May 2006 maillist, my test run only got flatten hierarchical 
netlist from gEDA netlisters. So I decided to experiment and wrote a 
crude bash script to generate a non-flatten hierarchical verilog 
netlist first as a proof of concept. The script is quite simple, it 
gathers hierarchical info from sch and sym files of each hierarchy 
levels in the design, generate a unique sym/sch list and invoke gEDA's 
gnetlist verilog to do each level of netlisting. As each level is 
processed, netlists of all hierarchical levels from different unique 
modules are concatinated into one netlist file. The script also 
generates a report file for the entire hierarchy of the design.

If you are interested, I'll be glad to post the script up. Ah, I have 
yet to learn the rule of posting files here; whether I should email it 
as an attached file, or I have to upload it elsewhere? Or is there a 
HOW-To that I can read to find out?

Best regards,
Paul Tan

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