gEDA-dev: iverilog: Reduction OR follows bitwise OR operator

[Stephan Boettcher]

Hi Steve,

The following code runs fine on iveriog, but some synthesizers
complain about it:

   wire      next;
   reg [1:0] worda;
   wire      read = next | |worda;

Is there an issue with the relevant standards, with some opportunity
for a warning by ivl?

Cheers
Stephan

>    reg [1:0] 		worda;
>    wire 		read = next | (|worda);     // 6-22, JC
>
> // Compile ERROR:  Reduction OR follows bitwise OR operator, consider using brackets to disambiguate.
> //   wire 		read = next | |worda;     // 6-22, JC