gEDA-dev: Icarus Verilog 0.8 - Bug(?)

[Ronny Obstei]

Hi Stephen Williams,
First of all, respect to your tool!

I got a problem with a for-loop, as you will see in the attached module. The 7th for-loop does not execute it's body. Could you eventually tell me why, or what I do wrong?

Thank you, best regards
Ronny Obstei
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1.) for(i=1; i<=10; i=i+1):
i=1 i=2 i=3 i=4 i=5 i=6 i=7 i=8 i=9 i=10 

2.) for(i=1+2; i<=10; i=i+1):
i=3 i=4 i=5 i=6 i=7 i=8 i=9 i=10 

3.) for(i=(1<<2); i<=10; i=i+1):
i=4 i=5 i=6 i=7 i=8 i=9 i=10 

4.) for(i=-(1<<2); i<=10; i=i+1):
i=-4 i=-3 i=-2 i=-1 i=0 i=1 i=2 i=3 i=4 i=5 i=6 i=7 i=8 i=9 i=10 

5.) for(i=1; i<=(1<<4); i=i+1):
i=1 i=2 i=3 i=4 i=5 i=6 i=7 i=8 i=9 i=10 i=11 i=12 i=13 i=14 i=15 i=16 

6.) for(i=(1<<2); i<=(1<<4); i=i+1):
i=4 i=5 i=6 i=7 i=8 i=9 i=10 i=11 i=12 i=13 i=14 i=15 i=16 

7.) for(i=-(1<<2); i<=(1<<2); i=i+1):


8.) for(i=-(1<<2); i!=(1<<2); i=i+1):
i=-4 i=-3 i=-2 i=-1 i=0 i=1 i=2 i=3