gEDA-dev: Blind and buried vias in PCB... who is doing what?

[Dan McMahill]

ldoolitt at recycle.lbl.gov wrote:
> Friends -
> 
> 
> On Tue, Jul 18, 2006 at 11:57:22AM +0200, Timmerman, Bert wrote:
>> If the file format of the pcb files is to be altered to accommodate for
>> BBV etc. then this may also be of interest to you.
> 
> I would also like to remind people in this context that there
> is a request for four states of joining (or not) of a via to
> the polygon (if any) per layer:
>   0: no connect
>   1: traditional X thermal
>   2: alternate + thermal
>   3: solid connection
> "Define the data structures, and the code will take care of itself."

I'm all for this.  Of course I tend to subscribe (somewhat) to the "if 
its not hard to solder to then its not grounded well enough" camp.  If 
it were me, I'd probably pick #3 for all my vias and #1/2 for my pins 
(as a action command of course).

-Dan