gEDA-dev: Blind and buried vias in PCB... who is doing what?

[Timmerman, Bert]

Hi Steve and all,

I felt a bit curious after reading your response, so I googled for
Buried Capacitance.

Just two interesting hits (out of the first 100, I felt lazy as well):

www.ddmconsulting.com/Design_Guides/bcguide.pdf 

and

www.ewh.ieee.org/r4/se_michigan/emcs/DL-ARCH-decoupling3.pdf 

The latter has some eye candy that explains what's going on, or isn't
;-)


Turns out that a better name would have been "Shared Capacitance" or
"Distributed Capacitance".

To me it looks like a special power/ground-plane pair with "special"
materials and a narrow distance between them.

Thx for your effort of asking anyway.

Kind regards,

Bert Timmerman.

-----Original Message-----
From: geda-dev-bounces at moria.seul.org
[mailto:geda-dev-bounces at moria.seul.org] On Behalf Of Steve Meier
Sent: Tuesday, July 18, 2006 7:14 PM
To: gEDA developer mailing list
Subject: Re: gEDA-dev: Blind and buried vias in PCB... who is doing
what?

Ok, I just asked and I was told that these are recommended by IPC and
military standards... Not a very satisfying answer. Looks like I will
have to dig deeper.

Steve Meier


> 
> Part 2)  I think looking at the technology capabilities for one fab
shop
> will give us a clue
> 
> http://hunterpcb.com/text/41/192/
> 
> Under the advanced production capability column see the entries for
rows
> Min. Outer Layer Via Land Size and Min. Inner Layer Via Land Size.
> 
> For the outer the minimum is 18 mills for the inner the minimum is 16
mills.
> 
> I don't know why but I do know who to ask and so I will. But the
> interesting thing is that the inner layer can take a smaller pad size
> then the outer layer opening up more realestate for traces.
> 




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