gEDA-dev: Blind and buried vias in PCB... who is doing what?

[ldoolitt at recycle.lbl.gov]

Friends -


On Tue, Jul 18, 2006 at 11:57:22AM +0200, Timmerman, Bert wrote:
> If the file format of the pcb files is to be altered to accommodate for
> BBV etc. then this may also be of interest to you.

I would also like to remind people in this context that there
is a request for four states of joining (or not) of a via to
the polygon (if any) per layer:
  0: no connect
  1: traditional X thermal
  2: alternate + thermal
  3: solid connection
"Define the data structures, and the code will take care of itself."

   - Larry