gEDA-dev: Blind and buried vias in PCB... who is doing what?

[Timmerman, Bert]

Hi Steve and all,

Has someone on the list ever experienced the need for "Buried
Capacitance (TM)" (BC) for decoupling purposes.

I read this the other day in a Design For Manufacturing Guidelines
document on
"http://www.pcblibraries.com/resources/files/GenDocs/DFM%20Guidelines.zi
p" page 21 and page 62 for Blind/Buried Vias (BBV).

Would the BC require the use of widened traces/rectangles/polygons in
"footprints" on the inner layers ?

And then there is the issue of padstacks: dimensions of top-pad,
inner-pad and bottom-pad are allways equal in the current implementation
of vias/plated through mounting holes (not to mention the
anti-pad/clearance on those layers), curently there isn't a proper way
to implement these features in the file format.

If the file format of the pcb files is to be altered to accommodate for
BBV etc. then this may also be of interest to you.

Just my EUR 0.02

Kind regards,

Bert Timmerman.

-----Original Message-----
From: geda-dev-bounces at moria.seul.org
[mailto:geda-dev-bounces at moria.seul.org] On Behalf Of Steve Meier
Sent: Sunday, July 16, 2006 12:12 AM
To: gEDA developer mailing list
Subject: Re: gEDA-dev: Blind and buried vias in PCB... who is doing
what?

I sure could use all the way down to micro vias for my current project.
I would also love having the ability to swap pins on these big fpga
devices. The good news is... that the increase in layers means I can
still get at all the pins of a 1000 and some count device even without
blind, buried and micro vias, however I am pretty sure it would still
help on the overal surface area requirements too.

Uhm, I think I was supposed to do some research for DJ on what fab
houses expect. So I think I am the one that has fallen doen on the task.

Steve M.


DJ Delorie wrote:
>I know of no current plans to add blind/buried via support to PCB.
>
>
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>geda-dev mailing list
>geda-dev at moria.seul.org
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