gEDA-dev: Thoughts on buses in gschem

[Cesar Strauss]

DJ Delorie wrote:
>> via a bus splitter to another piece of bus
>>     
>
> Hey, no fair invoking magic here :-)
>
> If different segments of a bus could be labelled differently, that
> would be cool.  Say, every three-way intersection allows for a label
> on one or three branches.  Two would be underspecified, but a label
> could be "inherited" from a pin.
>
>
> +-----------+                                           +-----------+
> |           |     [1]                      [2]          |           |
> |   A[0-23] |===============+===##======================| A[0-7]    |
> |           |               |   ||                      |           |
> |           |               |   ||
> |       BHE |----.          |   ||                 +-----------+
> |           |    |          |   ||    A[1-18]      |           |
> |           |    |          |   ``=================| A[0-17]   |
>                  |          |               A0     |           |
>                  |          `----------------------| BLE       |
>                  |                          BHE    |           |
>                  `---------------------------------| BHE       |
>                                                    |           |
>
> [1] This sub-bus is implicitly labelled "A[0-23]" from its pin
>     connection on the left.
>
> [2] This sub-bus is implicitly labelled "A[1-18]" from its pin
>     connection on the right.
>
> I'm OK with mandatory explicit labelling for the first pass, though.
>
>
> _______________________________________________
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> geda-dev at moria.seul.org
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>   
How about something based on C struct sintax:

+-----------+                                           +-----------+
|           | ADDR.A[0-23]  ADDR       ADDR.A[1-8]      |           |
|   A[0-23] |=============+=====##======================| A[0-7]    |
|           |             |     ||                      |           |
|           | ADDR.BHE    |     ||
|       BHE |-------------/     ||                 +-----------+
|           |                   ||    ADDR.A[1-18] |           |
|           |                   ||`================| A[0-17]   |
                                ||    ADDR.A[0]    |           |
                                ||`----------------| BLE       |
                                ||    ADDR.BHE     |           |
                                  `----------------| BHE       |
                                                   |           |
If bit ordering is important, use attributes:

                    CON_JTAG
                device=CONNECTOR[5]
 JTAG              +-----+
======    JTAG_OUT |     |
      `============|     |
   pin[0]=JTAG.TDO |     |
   pin[1]=JTAG.TDI |     |
   pin[2]=JTAG.TCK +-----+
   pin[3]=VCC
   pin[4]=GND


Cesar