gEDA-dev: Thoughts on buses in gschem

[Steve Meier]

Peter,

I am very interested in hierarchical bus structures. A lot of what I am
going to say is probably obvious.

Buses should be capable of grouping a large number of nets together.
Busrippers are used to join nets to buses. The question is which
position within a bus the joined net connects to?

I agree there needs to be some method for organizing the nets within a
bus and then for the busripper to selectively attach to one of the bus
contained nets.

I also think we need to be able to split sub-buses from buses. This
division of bus nets within a schematic page can also be accomplished
with a busripper but the busripper must have bus pins at both ends. A
standard busripper has a netpin on one side and a buspin on the other.

bus organization:

[D0..D31,A0..A64,WriteStrobe,ReadStrobe]

 represents actually a very simple bus but shows what might be rquired
expanding it to have number each and every net. would be:

[D0,D1,D2,D3,D4,D5,D6  get my drift?

suppose now I wish to split off the address nets

[D0..D31,A0..A64,WriteStrobe,ReadStrobe]    busripper(2 bus pins)   
[A0...A64]

Here it is important to note that the Net names did not change.



Bus net renaming:

Bus net renaming in my opinion takes place at the boundary of a symbol.
The symbol should have a buspin and the buspin should have an expected
net structure. Attaching a bus to the symbols bus pin connects each net
in order from within the symbol to the bus. For example:


Schematic      Bus-pin    Symbol
[D16..D31]     Bus-pin   [D0..D15]

This translates the high data nets into a symbol with represents say a
16 bit chunk of ram.
Thus the ram symbol may be reused.


to recap

[D0..D31,A0..A64,WriteStrobe,ReadStrobe]    busripper(2 bus pins)   
[D0...D15]    RAM - U1 BUS PIN    [D0..D15]

[D0..D31,A0..A64,WriteStrobe,ReadStrobe]    busripper(2 bus pins)   
[D16...D31]  RAM - U2  BUS PIN  [D0-D15]


By the way the real gory mess is not in gschem.... it is in gnetlist and
the processesing of complex hierarchical buses. On that note I am in the
process of deconstructing/reconstructing libgeda and gnetlist and since
iI need it for my current project...right now... I am working on this
task full time.

Code (buggy and incomplete at best) for my stuff can be found at:

www.alchemyresearch.com/geda-gschem-buses-20050313.zip

www.alchemyresearch.com/libgeda-buses-20050313.zip

www.alchemyresearch.com/mra_netlist_20060711_2.zip

Steve Meier


Peter TB Brett wrote:
> Hi folks,
>
> I want to share with you some (still rather sketchy) thoughts I've had
> on a better behaviour for buses in gschem. At the moment, buses in
> gschem are more or less graphical -- that is, in most examples of bus
> use, the buses could be quite happily omitted.  This e-mail is to
> explain how I think they could work usefully (for instance, it allows
> heirachical buses).
>
> (1) Make '[' and ']' special characters in netname attributes and
> pinlabel attributes.
>
> (2) Make the netname attribute of a bus a bit like an range in VHDL. 
> Example: "netname=MEMDATA[7:0]".  In this case, the bus expands out
> into 8 nets: MEMDATA7, MEMDATA6, MEMDATA5 ... MEMDATA0 *in that
> order*.  "netname=MEMDATA[0:7]" would expand in the opposite order
> (the distinction between 'to' and 'downto' in VHDL).  After expansion,
> those nets behave exactly like normal nets for the purpose of
> netlisting (as if the nets had been stacked on top of each other on
> the schematic).  A bus netname attribute without exactly one square
> bracket/colon expression generates a netlisting error.
>
> (3) Add a new "bus pin" atom. This would have attributes pinseq (a
> single number), pinlabel (a string similar to a bus's netname),
> pinnumber (a comma-separated list of pin numbers in the same order as
> the pinlabel expands), and pintype (a single pintype value). Example:
>
>  pinseq=2
>  pinlabel=DIN[0:7]
>  pinnumber=4,3,2,1,13,14,15,16
>  pintype=in
>
> A bus pin pinlabel attribute without exactly one square bracket/colon
> expression generates a netlisting error.
>
> (4) For slotted components, a slotdef where a bus pin must be
> specified would have a comma-separated sublist of pins enclosed in
> parentheses. Example: "slotdef=3:4,5,(6,7,10,11),8", where the pin
> with pinseq=3 is a 4-way bus pin.
>
> (5) Connecting a bus to a normal pin or a normal net to a bus
> generates a fatal error when netlisting.
>
> (5) Netlisting process: when a bus is connected to a bus pin, the
> netname and pinlabel attributes are expanded in the correct order, and
> are connected in pairs until the end of one of the ranges.  If the
> ranges have different lengths, it generates a warning when netlisting,
> and a DRC warning too.  Example: there is a bus with "netname=D[5:2]"
> and a symbol with a bus pin "pinlabel=IN[0:4]".  The nets would be
> connected as follows:
>
>  D5 - IN0
>  D4 - IN1
>  D3 - IN2
>  D2 - IN3
>
> IN4 would be NC, and a warning would be generated.
>
> (6) Netlisting process: when a symbol representing a subcircuit in a
> heirachical schematic has a bus pin, the bus is expanded and then
> connected to nets in the subcircuit just like normal nets, and just
> like normal nets, bus elements that have no corresponding subcircuit
> generate a warning.
>
> Any comments/suggestions/implementations gratefully received.
>
> Peter
>
>
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