gEDA-dev: Thoughts on buses in gschem

[Peter TB Brett]

DJ Delorie wrote:
>> Any comments/suggestions/implementations gratefully received.
>>     
>
> In my current project, I need to be able to do this:
>
> * The CPU uses A0..A23 for address bytes, with a !BHE for odd-words
>   (i.e. it's an inverse of A0), and D0..D15 for data.
>
> * The ethernet chip uses an 8-bit bus, so it uses A0..A7 and D0..D7.
>
> * The sram chip uses a 16 bit bus, so it uses A1..A18 (but the chip
>   labels them A0..A17) and D0..D15, with A0 and !BHE wired to control
>   pins.
Okay, so according to my scheme as suggested (you may need to draw this):

The CPU (U1) has bus pins A[0:23] and D[0:15], and a normal pin !BHE.

The eth chip (U2) has bus pins A[0:7] and D[0:7].

The sram chip (U3) has bus pins A[0:17] and D[0:15], with normal pins WS 
and !WS.

A piece of bus labelled A[0:23] connects U1/A[0:23] to U2/A[0:7], and 
via a bus splitter to another piece of bus labelled A[1:18], which 
itself connects to U3/A[0:17]. A piece of net labelled A0 connects from 
the original bus (via a bus splitter) to U3/WS.

A piece of bus labelled D[0:15] connects U1/D[0:15] to U2/D[0:7] and 
U3/D[0:15] with no bus splitters needed.

A piece of net connects U1/!BHE to U3/!WS.

Does that seem like it would make sense/be intuitive?

Peter