gEDA-dev: Thoughts on buses in gschem

[DJ Delorie]

> Any comments/suggestions/implementations gratefully received.

In my current project, I need to be able to do this:

* The CPU uses A0..A23 for address bytes, with a !BHE for odd-words
  (i.e. it's an inverse of A0), and D0..D15 for data.

* The ethernet chip uses an 8-bit bus, so it uses A0..A7 and D0..D7.

* The sram chip uses a 16 bit bus, so it uses A1..A18 (but the chip
  labels them A0..A17) and D0..D15, with A0 and !BHE wired to control
  pins.